d9277f249b
This follows the rest of the code base data structures, where we have a mutable data structure builder; once the data structure is constructed, it's immutable. This also makes the definition of instructions easier, and it paves the way for defining immediate variants.
119 lines
3.7 KiB
Rust
119 lines
3.7 KiB
Rust
use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::instructions::InstructionGroupBuilder;
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
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use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
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use crate::shared::types::Float::{F32, F64};
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use crate::shared::types::Int::{I32, I64};
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use crate::shared::Definitions as SharedDefinitions;
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fn define_settings(shared: &SettingGroup) -> SettingGroup {
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let mut setting = SettingGroupBuilder::new("riscv");
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let supports_m = setting.add_bool(
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"supports_m",
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"CPU supports the 'M' extension (mul/div)",
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false,
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);
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let supports_a = setting.add_bool(
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"supports_a",
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"CPU supports the 'A' extension (atomics)",
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false,
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);
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let supports_f = setting.add_bool(
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"supports_f",
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"CPU supports the 'F' extension (float)",
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false,
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);
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let supports_d = setting.add_bool(
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"supports_d",
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"CPU supports the 'D' extension (double)",
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false,
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);
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let enable_m = setting.add_bool(
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"enable_m",
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"Enable the use of 'M' instructions if available",
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true,
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);
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setting.add_bool(
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"enable_e",
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"Enable the 'RV32E' instruction set with only 16 registers",
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false,
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);
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let shared_enable_atomics = shared.get_bool("enable_atomics");
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let shared_enable_float = shared.get_bool("enable_float");
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let shared_enable_simd = shared.get_bool("enable_simd");
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setting.add_predicate("use_m", predicate!(supports_m && enable_m));
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setting.add_predicate("use_a", predicate!(supports_a && shared_enable_atomics));
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setting.add_predicate("use_f", predicate!(supports_f && shared_enable_float));
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setting.add_predicate("use_d", predicate!(supports_d && shared_enable_float));
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setting.add_predicate(
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"full_float",
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predicate!(shared_enable_simd && supports_f && supports_d),
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);
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setting.finish()
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}
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fn define_registers() -> IsaRegs {
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let mut regs = IsaRegsBuilder::new();
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let builder = RegBankBuilder::new("IntRegs", "x")
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.units(32)
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.track_pressure(true);
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let int_regs = regs.add_bank(builder);
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let builder = RegBankBuilder::new("FloatRegs", "f")
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.units(32)
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.track_pressure(true);
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let float_regs = regs.add_bank(builder);
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let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
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regs.add_class(builder);
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let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
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regs.add_class(builder);
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regs.finish()
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}
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pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = define_settings(&shared_defs.settings);
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let regs = define_registers();
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let inst_group = InstructionGroupBuilder::new(
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"riscv",
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"riscv specific instruction set",
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&shared_defs.format_registry,
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)
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.finish();
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// CPU modes for 32-bit and 64-bit operation.
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let mut rv_32 = CpuMode::new("RV32");
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let mut rv_64 = CpuMode::new("RV64");
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let expand = shared_defs.transform_groups.by_name("expand");
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let narrow = shared_defs.transform_groups.by_name("narrow");
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rv_32.legalize_monomorphic(expand);
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rv_32.legalize_default(narrow);
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rv_32.legalize_type(I32, expand);
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rv_32.legalize_type(F32, expand);
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rv_32.legalize_type(F64, expand);
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rv_64.legalize_monomorphic(expand);
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rv_64.legalize_default(narrow);
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rv_64.legalize_type(I32, expand);
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rv_64.legalize_type(I64, expand);
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rv_64.legalize_type(F32, expand);
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rv_64.legalize_type(F64, expand);
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let cpu_modes = vec![rv_32, rv_64];
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TargetIsa::new("riscv", inst_group, settings, regs, cpu_modes)
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}
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