Remove reg_universe method from MachBackend and MachInst

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -2017,10 +2017,6 @@ impl MachInst for Inst {
         }
     }
 
-    fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
-        create_reg_universe(flags)
-    }
-
     fn worst_case_size() -> CodeOffset {
         // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
         // an 8-instruction sequence (saturating int-to-float conversions) with three embedded

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -58,7 +58,7 @@ impl AArch64Backend {
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone());
         let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?);
-        compile::compile::<AArch64Backend>(func, self, abi, self.reg_universe(), emit_info)
+        compile::compile::<AArch64Backend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
 
@@ -110,10 +110,6 @@ impl MachBackend for AArch64Backend {
         self.isa_flags.iter().collect()
     }
 
-    fn reg_universe(&self) -> &RealRegUniverse {
-        &self.reg_universe
-    }
-
     fn unsigned_add_overflow_condition(&self) -> IntCC {
         // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on
         // overflow of an add.

cranelift/codegen/src/isa/arm32/inst/mod.rs

@@ -859,10 +859,6 @@ impl MachInst for Inst {
         }
     }
 
-    fn reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
-        create_reg_universe()
-    }
-
     fn worst_case_size() -> CodeOffset {
         // It inst with four 32-bit instructions
         2 + 4 * 4

cranelift/codegen/src/isa/arm32/mod.rs

@@ -49,7 +49,7 @@ impl Arm32Backend {
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone());
         let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
-        compile::compile::<Arm32Backend>(func, self, abi, self.reg_universe(), emit_info)
+        compile::compile::<Arm32Backend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
 
@@ -100,10 +100,6 @@ impl MachBackend for Arm32Backend {
         Vec::new()
     }
 
-    fn reg_universe(&self) -> &RealRegUniverse {
-        &self.reg_universe
-    }
-
     fn unsigned_add_overflow_condition(&self) -> IntCC {
         // Carry flag set.
         IntCC::UnsignedGreaterThanOrEqual

cranelift/codegen/src/isa/s390x/inst/mod.rs

@@ -2507,10 +2507,6 @@ impl MachInst for Inst {
         }
     }
 
-    fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
-        create_reg_universe(flags)
-    }
-
     fn worst_case_size() -> CodeOffset {
         // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
         // an 8-instruction sequence (saturating int-to-float conversions) with three embedded

cranelift/codegen/src/isa/s390x/mod.rs

@@ -61,7 +61,7 @@ impl S390xBackend {
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
         let abi = Box::new(abi::S390xABICallee::new(func, flags)?);
-        compile::compile::<S390xBackend>(func, self, abi, self.reg_universe(), emit_info)
+        compile::compile::<S390xBackend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
 
@@ -113,10 +113,6 @@ impl MachBackend for S390xBackend {
         self.isa_flags.iter().collect()
     }
 
-    fn reg_universe(&self) -> &RealRegUniverse {
-        &self.reg_universe
-    }
-
     fn unsigned_add_overflow_condition(&self) -> IntCC {
         // The ADD LOGICAL family of instructions set the condition code
         // differently from normal comparisons, in a way that cannot be

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -7,7 +7,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec;
 use crate::isa::x64::settings as x64_settings;
 use crate::isa::CallConv;
 use crate::machinst::*;
-use crate::{settings, settings::Flags, CodegenError, CodegenResult};
+use crate::{settings, CodegenError, CodegenResult};
 use alloc::boxed::Box;
 use alloc::vec::Vec;
 use regalloc::{
@@ -26,7 +26,7 @@ pub mod regs;
 pub mod unwind;
 
 use args::*;
-use regs::{create_reg_universe_systemv, show_ireg_sized};
+use regs::show_ireg_sized;
 
 //=============================================================================
 // Instructions (top level): definition
@@ -3256,10 +3256,6 @@ impl MachInst for Inst {
         ret
     }
 
-    fn reg_universe(flags: &Flags) -> RealRegUniverse {
-        create_reg_universe_systemv(flags)
-    }
-
     fn worst_case_size() -> CodeOffset {
         15
     }

cranelift/codegen/src/isa/x64/mod.rs

@@ -50,7 +50,7 @@ impl X64Backend {
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
         let abi = Box::new(abi::X64ABICallee::new(&func, flags)?);
-        compile::compile::<Self>(&func, self, abi, self.reg_universe(), emit_info)
+        compile::compile::<Self>(&func, self, abi, &self.reg_universe, emit_info)
     }
 }
 
@@ -102,10 +102,6 @@ impl MachBackend for X64Backend {
         &self.triple
     }
 
-    fn reg_universe(&self) -> &RealRegUniverse {
-        &self.reg_universe
-    }
-
     fn unsigned_add_overflow_condition(&self) -> IntCC {
         // Unsigned `<`; this corresponds to the carry flag set on x86, which
         // indicates an add has overflowed.

cranelift/codegen/src/machinst/mod.rs

@@ -181,9 +181,6 @@ pub trait MachInst: Clone + Debug {
     /// the instruction must have a nonzero size if preferred_size is nonzero.
     fn gen_nop(preferred_size: usize) -> Self;
 
-    /// Get the register universe for this backend.
-    fn reg_universe(flags: &Flags) -> RealRegUniverse;
-
     /// Align a basic block offset (from start of function).  By default, no
     /// alignment occurs.
     fn align_basic_block(offset: CodeOffset) -> CodeOffset {
@@ -388,9 +385,6 @@ pub trait MachBackend {
     /// Return name for this backend.
     fn name(&self) -> &'static str;
 
-    /// Return the register universe for this backend.
-    fn reg_universe(&self) -> &RealRegUniverse;
-
     /// Machine-specific condcode info needed by TargetIsa.
     /// Condition that will be true when an IaddIfcout overflows.
     fn unsigned_add_overflow_condition(&self) -> IntCC;