From d50f27e8f97674ba0353cc5eae0c46c54e37bcea Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Tue, 4 Jan 2022 19:28:10 +0100 Subject: [PATCH] Remove reg_universe method from MachBackend and MachInst --- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 4 ---- cranelift/codegen/src/isa/aarch64/mod.rs | 6 +----- cranelift/codegen/src/isa/arm32/inst/mod.rs | 4 ---- cranelift/codegen/src/isa/arm32/mod.rs | 6 +----- cranelift/codegen/src/isa/s390x/inst/mod.rs | 4 ---- cranelift/codegen/src/isa/s390x/mod.rs | 6 +----- cranelift/codegen/src/isa/x64/inst/mod.rs | 8 ++------ cranelift/codegen/src/isa/x64/mod.rs | 6 +----- cranelift/codegen/src/machinst/mod.rs | 6 ------ 9 files changed, 6 insertions(+), 44 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 83d878b746..66a6e536d5 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -2017,10 +2017,6 @@ impl MachInst for Inst { } } - fn reg_universe(flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe(flags) - } - fn worst_case_size() -> CodeOffset { // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of // an 8-instruction sequence (saturating int-to-float conversions) with three embedded diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 47ccbeb181..95987b1f0c 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -58,7 +58,7 @@ impl AArch64Backend { ) -> CodegenResult> { let emit_info = EmitInfo::new(flags.clone()); let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?); - compile::compile::(func, self, abi, self.reg_universe(), emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } @@ -110,10 +110,6 @@ impl MachBackend for AArch64Backend { self.isa_flags.iter().collect() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on // overflow of an add. diff --git a/cranelift/codegen/src/isa/arm32/inst/mod.rs b/cranelift/codegen/src/isa/arm32/inst/mod.rs index 8151eab818..7cba5d6c1c 100644 --- a/cranelift/codegen/src/isa/arm32/inst/mod.rs +++ b/cranelift/codegen/src/isa/arm32/inst/mod.rs @@ -859,10 +859,6 @@ impl MachInst for Inst { } } - fn reg_universe(_flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe() - } - fn worst_case_size() -> CodeOffset { // It inst with four 32-bit instructions 2 + 4 * 4 diff --git a/cranelift/codegen/src/isa/arm32/mod.rs b/cranelift/codegen/src/isa/arm32/mod.rs index 85d77cc99c..876c74fb45 100644 --- a/cranelift/codegen/src/isa/arm32/mod.rs +++ b/cranelift/codegen/src/isa/arm32/mod.rs @@ -49,7 +49,7 @@ impl Arm32Backend { // block layout and finalizes branches. The result is ready for binary emission. let emit_info = EmitInfo::new(flags.clone()); let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?); - compile::compile::(func, self, abi, self.reg_universe(), emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } @@ -100,10 +100,6 @@ impl MachBackend for Arm32Backend { Vec::new() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // Carry flag set. IntCC::UnsignedGreaterThanOrEqual diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 74406cd8df..b48b4fb2a7 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -2507,10 +2507,6 @@ impl MachInst for Inst { } } - fn reg_universe(flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe(flags) - } - fn worst_case_size() -> CodeOffset { // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of // an 8-instruction sequence (saturating int-to-float conversions) with three embedded diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index e6be4e33f0..63a5762fe7 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -61,7 +61,7 @@ impl S390xBackend { ) -> CodegenResult> { let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone()); let abi = Box::new(abi::S390xABICallee::new(func, flags)?); - compile::compile::(func, self, abi, self.reg_universe(), emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } @@ -113,10 +113,6 @@ impl MachBackend for S390xBackend { self.isa_flags.iter().collect() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // The ADD LOGICAL family of instructions set the condition code // differently from normal comparisons, in a way that cannot be diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 3ab8f89b12..ea036c95b5 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -7,7 +7,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::settings as x64_settings; use crate::isa::CallConv; use crate::machinst::*; -use crate::{settings, settings::Flags, CodegenError, CodegenResult}; +use crate::{settings, CodegenError, CodegenResult}; use alloc::boxed::Box; use alloc::vec::Vec; use regalloc::{ @@ -26,7 +26,7 @@ pub mod regs; pub mod unwind; use args::*; -use regs::{create_reg_universe_systemv, show_ireg_sized}; +use regs::show_ireg_sized; //============================================================================= // Instructions (top level): definition @@ -3256,10 +3256,6 @@ impl MachInst for Inst { ret } - fn reg_universe(flags: &Flags) -> RealRegUniverse { - create_reg_universe_systemv(flags) - } - fn worst_case_size() -> CodeOffset { 15 } diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index 3fd229ea9d..6907ac81ba 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -50,7 +50,7 @@ impl X64Backend { // block layout and finalizes branches. The result is ready for binary emission. let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone()); let abi = Box::new(abi::X64ABICallee::new(&func, flags)?); - compile::compile::(&func, self, abi, self.reg_universe(), emit_info) + compile::compile::(&func, self, abi, &self.reg_universe, emit_info) } } @@ -102,10 +102,6 @@ impl MachBackend for X64Backend { &self.triple } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // Unsigned `<`; this corresponds to the carry flag set on x86, which // indicates an add has overflowed. diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index de491f2ace..1bd4f679ce 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -181,9 +181,6 @@ pub trait MachInst: Clone + Debug { /// the instruction must have a nonzero size if preferred_size is nonzero. fn gen_nop(preferred_size: usize) -> Self; - /// Get the register universe for this backend. - fn reg_universe(flags: &Flags) -> RealRegUniverse; - /// Align a basic block offset (from start of function). By default, no /// alignment occurs. fn align_basic_block(offset: CodeOffset) -> CodeOffset { @@ -388,9 +385,6 @@ pub trait MachBackend { /// Return name for this backend. fn name(&self) -> &'static str; - /// Return the register universe for this backend. - fn reg_universe(&self) -> &RealRegUniverse; - /// Machine-specific condcode info needed by TargetIsa. /// Condition that will be true when an IaddIfcout overflows. fn unsigned_add_overflow_condition(&self) -> IntCC;