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Add subtract and logical instruction encodings to Intel-32.

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Also add versions with 8-bit and 32-bit immediate operands.
This commit is contained in:
Jakob Stoklund Olesen
2017-05-12 10:35:18 -07:00
parent 3aaa8b2f91
commit c998df6274
5 changed files with 117 additions and 10 deletions
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70
filetests/isa/intel/binary32.cton
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@@ -18,21 +18,79 @@ ebb0:
[-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1
; asm: addl %ecx, %esi
[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
; asm: subl %esi, %ecx
[-,%rcx] v12 = isub v1, v2 ; bin: 29 f1
; asm: subl %ecx, %esi
[-,%rsi] v13 = isub v2, v1 ; bin: 29 ce
; asm: andl %esi, %ecx
[-,%rcx] v14 = band v1, v2 ; bin: 21 f1
; asm: andl %ecx, %esi
[-,%rsi] v15 = band v2, v1 ; bin: 21 ce
; asm: orl %esi, %ecx
[-,%rcx] v16 = bor v1, v2 ; bin: 09 f1
; asm: orl %ecx, %esi
[-,%rsi] v17 = bor v2, v1 ; bin: 09 ce
; asm: xorl %esi, %ecx
[-,%rcx] v18 = bxor v1, v2 ; bin: 31 f1
; asm: xorl %ecx, %esi
[-,%rsi] v19 = bxor v2, v1 ; bin: 31 ce
; Dynamic shifts take the shift amount in %rcx.
; asm: shll %cl, %esi
[-,%rsi] v12 = ishl v2, v1 ; bin: d3 e6
[-,%rsi] v20 = ishl v2, v1 ; bin: d3 e6
; asm: shll %cl, %ecx
[-,%rcx] v13 = ishl v1, v1 ; bin: d3 e1
[-,%rcx] v21 = ishl v1, v1 ; bin: d3 e1
; asm: shrl %cl, %esi
[-,%rsi] v14 = ushr v2, v1 ; bin: d3 ee
[-,%rsi] v22 = ushr v2, v1 ; bin: d3 ee
; asm: shrl %cl, %ecx
[-,%rcx] v15 = ushr v1, v1 ; bin: d3 e9
[-,%rcx] v23 = ushr v1, v1 ; bin: d3 e9
; asm: sarl %cl, %esi
[-,%rsi] v16 = sshr v2, v1 ; bin: d3 fe
[-,%rsi] v24 = sshr v2, v1 ; bin: d3 fe
; asm: sarl %cl, %ecx
[-,%rcx] v17 = sshr v1, v1 ; bin: d3 f9
[-,%rcx] v25 = sshr v1, v1 ; bin: d3 f9
; Integer Register - Immediate 8-bit operations.
; The 8-bit immediate is sign-extended.
; asm: addl $-128, %ecx
[-,%rcx] v30 = iadd_imm v1, -128 ; bin: 83 c1 80
; asm: addl $10, %esi
[-,%rsi] v31 = iadd_imm v2, 10 ; bin: 83 c6 0a
; asm: andl $-128, %ecx
[-,%rcx] v32 = band_imm v1, -128 ; bin: 83 e1 80
; asm: andl $10, %esi
[-,%rsi] v33 = band_imm v2, 10 ; bin: 83 e6 0a
; asm: orl $-128, %ecx
[-,%rcx] v34 = bor_imm v1, -128 ; bin: 83 c9 80
; asm: orl $10, %esi
[-,%rsi] v35 = bor_imm v2, 10 ; bin: 83 ce 0a
; asm: xorl $-128, %ecx
[-,%rcx] v36 = bxor_imm v1, -128 ; bin: 83 f1 80
; asm: xorl $10, %esi
[-,%rsi] v37 = bxor_imm v2, 10 ; bin: 83 f6 0a
; Integer Register - Immediate 32-bit operations.
; asm: addl $-128000, %ecx
[-,%rcx] v40 = iadd_imm v1, -128000 ; bin: 81 c1 fffe0c00
; asm: addl $1000000, %esi
[-,%rsi] v41 = iadd_imm v2, 1000000 ; bin: 81 c6 000f4240
; asm: andl $-128000, %ecx
[-,%rcx] v42 = band_imm v1, -128000 ; bin: 81 e1 fffe0c00
; asm: andl $1000000, %esi
[-,%rsi] v43 = band_imm v2, 1000000 ; bin: 81 e6 000f4240
; asm: orl $-128000, %ecx
[-,%rcx] v44 = bor_imm v1, -128000 ; bin: 81 c9 fffe0c00
; asm: orl $1000000, %esi
[-,%rsi] v45 = bor_imm v2, 1000000 ; bin: 81 ce 000f4240
; asm: xorl $-128000, %ecx
[-,%rcx] v46 = bxor_imm v1, -128000 ; bin: 81 f1 fffe0c00
; asm: xorl $1000000, %esi
[-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240
return
}

16
lib/cretonne/meta/isa/intel/encodings.py
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@@ -4,10 +4,24 @@ Intel Encodings.
from __future__ import absolute_import
from base import instructions as base
from .defs import I32
from .recipes import Op1rr, Op1rc
from .recipes import Op1rr, Op1rc, Op1rib, Op1rid
from .recipes import OP
I32.enc(base.iadd.i32, Op1rr, OP(0x01))
I32.enc(base.isub.i32, Op1rr, OP(0x29))
I32.enc(base.band.i32, Op1rr, OP(0x21))
I32.enc(base.bor.i32, Op1rr, OP(0x09))
I32.enc(base.bxor.i32, Op1rr, OP(0x31))
# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
for inst, r in [
(base.iadd_imm.i32, 0),
(base.band_imm.i32, 4),
(base.bor_imm.i32, 1),
(base.bxor_imm.i32, 6)]:
I32.enc(inst, Op1rib, OP(0x83, rrr=r))
I32.enc(inst, Op1rid, OP(0x81, rrr=r))
# 32-bit shifts and rotates.
# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit

14
lib/cretonne/meta/isa/intel/recipes.py
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@@ -3,8 +3,8 @@ Intel Encoding recipes.
"""
from __future__ import absolute_import
from cdsl.isa import EncRecipe
# from cdsl.predicates import IsSignedInt
from base.formats import Binary
from cdsl.predicates import IsSignedInt
from base.formats import Binary, BinaryImm
from .registers import GPR
# Opcode representation.
@@ -68,3 +68,13 @@ Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
# XX /n with one arg in %rcx, for shifts.
Op1rc = EncRecipe('Op1rc', Binary, size=2, ins=(GPR, GPR.rcx), outs=0)
# XX /n ib with 8-bit immediate sign-extended.
Op1rib = EncRecipe(
'Op1rib', BinaryImm, size=3, ins=GPR, outs=0,
instp=IsSignedInt(BinaryImm.imm, 8))
# XX /n id with 32-bit immediate sign-extended.
Op1rid = EncRecipe(
'Op1rid', BinaryImm, size=6, ins=GPR, outs=0,
instp=IsSignedInt(BinaryImm.imm, 32))

24
lib/cretonne/src/isa/intel/binemit.rs
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@@ -53,3 +53,27 @@ fn recipe_op1rc<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
panic!("Expected Binary format: {:?}", func.dfg[inst]);
}
}
fn recipe_op1rib<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
let bits = func.encodings[inst].bits();
put_op1(bits, sink);
modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
let imm: i64 = imm.into();
sink.put1(imm as u8);
} else {
panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
}
}
fn recipe_op1rid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
let bits = func.encodings[inst].bits();
put_op1(bits, sink);
modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
let imm: i64 = imm.into();
sink.put4(imm as u32);
} else {
panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
}
}

3
lib/cretonne/src/isa/intel/enc_tables.rs
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@@ -1,11 +1,12 @@
//! Encoding tables for Intel ISAs.
use ir::{Opcode, InstructionData};
use ir::types;
use ir::{Opcode, InstructionData};
use isa::EncInfo;
use isa::constraints::*;
use isa::enc_tables::{Level1Entry, Level2Entry};
use isa::encoding::RecipeSizing;
use predicates;
use super::registers::*;
include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));