97 lines
3.5 KiB
Plaintext
97 lines
3.5 KiB
Plaintext
; binary emission of 32-bit code.
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test binemit
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isa intel
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32.cton | llvm-mc -show-encoding -triple=i386
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;
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function I32() {
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ebb0:
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[-,%rcx] v1 = iconst.i32 1
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[-,%rsi] v2 = iconst.i32 2
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; Integer Register-Register Operations.
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; asm: addl %esi, %ecx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1
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; asm: addl %ecx, %esi
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[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
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; asm: subl %esi, %ecx
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[-,%rcx] v12 = isub v1, v2 ; bin: 29 f1
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; asm: subl %ecx, %esi
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[-,%rsi] v13 = isub v2, v1 ; bin: 29 ce
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; asm: andl %esi, %ecx
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[-,%rcx] v14 = band v1, v2 ; bin: 21 f1
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; asm: andl %ecx, %esi
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[-,%rsi] v15 = band v2, v1 ; bin: 21 ce
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; asm: orl %esi, %ecx
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[-,%rcx] v16 = bor v1, v2 ; bin: 09 f1
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; asm: orl %ecx, %esi
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[-,%rsi] v17 = bor v2, v1 ; bin: 09 ce
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; asm: xorl %esi, %ecx
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[-,%rcx] v18 = bxor v1, v2 ; bin: 31 f1
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; asm: xorl %ecx, %esi
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[-,%rsi] v19 = bxor v2, v1 ; bin: 31 ce
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; Dynamic shifts take the shift amount in %rcx.
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; asm: shll %cl, %esi
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[-,%rsi] v20 = ishl v2, v1 ; bin: d3 e6
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; asm: shll %cl, %ecx
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[-,%rcx] v21 = ishl v1, v1 ; bin: d3 e1
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; asm: shrl %cl, %esi
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[-,%rsi] v22 = ushr v2, v1 ; bin: d3 ee
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; asm: shrl %cl, %ecx
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[-,%rcx] v23 = ushr v1, v1 ; bin: d3 e9
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; asm: sarl %cl, %esi
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[-,%rsi] v24 = sshr v2, v1 ; bin: d3 fe
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; asm: sarl %cl, %ecx
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[-,%rcx] v25 = sshr v1, v1 ; bin: d3 f9
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; Integer Register - Immediate 8-bit operations.
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; The 8-bit immediate is sign-extended.
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; asm: addl $-128, %ecx
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[-,%rcx] v30 = iadd_imm v1, -128 ; bin: 83 c1 80
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; asm: addl $10, %esi
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[-,%rsi] v31 = iadd_imm v2, 10 ; bin: 83 c6 0a
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; asm: andl $-128, %ecx
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[-,%rcx] v32 = band_imm v1, -128 ; bin: 83 e1 80
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; asm: andl $10, %esi
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[-,%rsi] v33 = band_imm v2, 10 ; bin: 83 e6 0a
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; asm: orl $-128, %ecx
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[-,%rcx] v34 = bor_imm v1, -128 ; bin: 83 c9 80
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; asm: orl $10, %esi
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[-,%rsi] v35 = bor_imm v2, 10 ; bin: 83 ce 0a
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; asm: xorl $-128, %ecx
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[-,%rcx] v36 = bxor_imm v1, -128 ; bin: 83 f1 80
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; asm: xorl $10, %esi
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[-,%rsi] v37 = bxor_imm v2, 10 ; bin: 83 f6 0a
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; Integer Register - Immediate 32-bit operations.
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; asm: addl $-128000, %ecx
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[-,%rcx] v40 = iadd_imm v1, -128000 ; bin: 81 c1 fffe0c00
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; asm: addl $1000000, %esi
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[-,%rsi] v41 = iadd_imm v2, 1000000 ; bin: 81 c6 000f4240
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; asm: andl $-128000, %ecx
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[-,%rcx] v42 = band_imm v1, -128000 ; bin: 81 e1 fffe0c00
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; asm: andl $1000000, %esi
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[-,%rsi] v43 = band_imm v2, 1000000 ; bin: 81 e6 000f4240
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; asm: orl $-128000, %ecx
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[-,%rcx] v44 = bor_imm v1, -128000 ; bin: 81 c9 fffe0c00
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; asm: orl $1000000, %esi
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[-,%rsi] v45 = bor_imm v2, 1000000 ; bin: 81 ce 000f4240
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; asm: xorl $-128000, %ecx
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[-,%rcx] v46 = bxor_imm v1, -128000 ; bin: 81 f1 fffe0c00
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; asm: xorl $1000000, %esi
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[-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240
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return
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}
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