Add a CPUMode meta-language class.
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@@ -228,6 +228,8 @@ instruction. Both RISC-V and ARMv8's T32 mode have 32-bit encodings of all
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instructions with 16-bit encodings available for some opcodes if certain
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constraints are satisfied.
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.. autoclass:: CPUMode
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Encodings are guarded by :term:`sub-target predicate`\s. For example, the RISC-V
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"C" extension which specifies the compressed encodings may not be supported, and
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a predicate would be used to disable all of the 16-bit encodings in that case.
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