diff --git a/docs/metaref.rst b/docs/metaref.rst
index 058cc6459f..b7f607f91f 100644
--- a/docs/metaref.rst
+++ b/docs/metaref.rst
@@ -228,6 +228,8 @@ instruction. Both RISC-V and ARMv8's T32 mode have 32-bit encodings of all
 instructions with 16-bit encodings available for some opcodes if certain
 constraints are satisfied.
 
+.. autoclass:: CPUMode
+
 Encodings are guarded by :term:`sub-target predicate`\s. For example, the RISC-V
 "C" extension which specifies the compressed encodings may not be supported, and
 a predicate would be used to disable all of the 16-bit encodings in that case.
diff --git a/meta/cretonne/__init__.py b/meta/cretonne/__init__.py
index 9660e9e602..d5e6530280 100644
--- a/meta/cretonne/__init__.py
+++ b/meta/cretonne/__init__.py
@@ -656,6 +656,23 @@ class Target(object):
         self.name = name
         self.instruction_groups = instrution_groups
 
+
+class CPUMode(object):
+    """
+    A CPU mode determines which instruction encodings are active.
+
+    All instruction encodings are associated with exactly one `CPUMode`, and
+    all CPU modes are associated with exactly one `Target`.
+
+    :param name: Short mnemonic name for the CPU mode.
+    :param target: Associated `Target`.
+    """
+
+    def __init__(self, name, target):
+        self.name = name
+        self.target = target
+
+
 # Import the fixed instruction formats now so they can be added to the
 # registry.
 importlib.import_module('cretonne.formats')
diff --git a/meta/target/riscv/__init__.py b/meta/target/riscv/__init__.py
index bdb5b63091..918602c78e 100644
--- a/meta/target/riscv/__init__.py
+++ b/meta/target/riscv/__init__.py
@@ -25,7 +25,11 @@ RV32G / RV64G
 
 """
 
-from cretonne import Target
+from cretonne import Target, CPUMode
 import cretonne.base
 
 target = Target('riscv', [cretonne.base.instructions])
+
+# CPU modes for 32-bit and 64-bit operation.
+RV32 = CPUMode('RV32', target)
+RV64 = CPUMode('RV64', target)