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Add an empty isa/riscv module scaffold.

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Targeted ISAs will be defined as sub-modules of isa.
This commit is contained in:
Jakob Stoklund Olesen
2016-08-04 11:39:25 -07:00
parent 5bd2117ad7
commit c47c524017
3 changed files with 8 additions and 0 deletions
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src/libcretonne/isa/riscv/mod.rs Normal file
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//! RISC-V Instruction Set Architecture.