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cranelift: remove load_complex and store_complex (#3976)

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This change removes all variants of `load*_complex` and `store*_complex`
from Cranelift; this is a breaking change to the instructions exposed by
CLIF. The complete list of instructions removed is: `load_complex`,
`store_complex`, `uload8_complex`, `sload8_complex`, `istore8_complex`,
`sload8_complex`, `uload16_complex`, `sload16_complex`,
`istore16_complex`, `uload32_complex`, `sload32_complex`,
`istore32_complex`, `uload8x8_complex`, `sload8x8_complex`,
`sload16x4_complex`, `uload16x4_complex`, `uload32x2_complex`,
`sload32x2_complex`.

The rationale for this removal is that the Cranelift backend now has the
ability to pattern-match multiple upstream additions in order to
calculate the address to access. Previously, this was not possible so
the `*_complex` instructions were needed. Over time, these instructions
have fallen out of use in this repository, making the additional
overhead of maintaining them a chore.
This commit is contained in:
Andrew Brown
2022-03-31 10:05:10 -07:00
committed by GitHub
parent c8daf0b8db
commit bd6fe11ca9
20 changed files with 51 additions and 892 deletions
Download Patch File Download Diff File Expand all files Collapse all files

121
cranelift/codegen/src/clif.isle
View File

@@ -148,39 +148,22 @@
UsubSat
SsubSat
Load
LoadComplex
Store
StoreComplex
Uload8
Uload8Complex
Sload8
Sload8Complex
Istore8
Istore8Complex
Uload16
Uload16Complex
Sload16
Sload16Complex
Istore16
Istore16Complex
Uload32
Uload32Complex
Sload32
Sload32Complex
Istore32
Istore32Complex
Uload8x8
Uload8x8Complex
Sload8x8
Sload8x8Complex
Uload16x4
Uload16x4Complex
Sload16x4
Sload16x4Complex
Uload32x2
Uload32x2Complex
Sload32x2
Sload32x2Complex
StackLoad
StackStore
StackAddr
@@ -364,7 +347,6 @@
(IntSelect (opcode Opcode) (args ValueArray3) (cond IntCC))
(Jump (opcode Opcode) (args ValueList) (destination Block))
(Load (opcode Opcode) (arg Value) (flags MemFlags) (offset Offset32))
(LoadComplex (opcode Opcode) (args ValueList) (flags MemFlags) (offset Offset32))
(LoadNoOffset (opcode Opcode) (arg Value) (flags MemFlags))
(MultiAry (opcode Opcode) (args ValueList))
(NullAry (opcode Opcode))
@@ -372,7 +354,6 @@
(StackLoad (opcode Opcode) (stack_slot StackSlot) (offset Offset32))
(StackStore (opcode Opcode) (arg Value) (stack_slot StackSlot) (offset Offset32))
(Store (opcode Opcode) (args ValueArray2) (flags MemFlags) (offset Offset32))
(StoreComplex (opcode Opcode) (args ValueList) (flags MemFlags) (offset Offset32))
(StoreNoOffset (opcode Opcode) (args ValueArray2) (flags MemFlags))
(TableAddr (opcode Opcode) (arg Value) (table Table) (offset Offset32))
(Ternary (opcode Opcode) (args ValueArray3))
@@ -594,204 +575,102 @@
(inst_data (InstructionData.Load (Opcode.Load) p MemFlags Offset))
)
(decl load_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(load_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.LoadComplex) (value_list_slice args) MemFlags Offset))
)
(decl store (MemFlags Value Value Offset32) Inst)
(extractor
(store MemFlags x p Offset)
(inst_data (InstructionData.Store (Opcode.Store) (value_array_2 x p) MemFlags Offset))
)
(decl store_complex (MemFlags Value ValueSlice Offset32) Inst)
(extractor
(store_complex MemFlags x args Offset)
(inst_data (InstructionData.StoreComplex (Opcode.StoreComplex) (unwrap_head_value_list_1 x args) MemFlags Offset))
)
(decl uload8 (MemFlags Value Offset32) Inst)
(extractor
(uload8 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload8) p MemFlags Offset))
)
(decl uload8_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload8_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload8Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload8 (MemFlags Value Offset32) Inst)
(extractor
(sload8 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload8) p MemFlags Offset))
)
(decl sload8_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload8_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload8Complex) (value_list_slice args) MemFlags Offset))
)
(decl istore8 (MemFlags Value Value Offset32) Inst)
(extractor
(istore8 MemFlags x p Offset)
(inst_data (InstructionData.Store (Opcode.Istore8) (value_array_2 x p) MemFlags Offset))
)
(decl istore8_complex (MemFlags Value ValueSlice Offset32) Inst)
(extractor
(istore8_complex MemFlags x args Offset)
(inst_data (InstructionData.StoreComplex (Opcode.Istore8Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
)
(decl uload16 (MemFlags Value Offset32) Inst)
(extractor
(uload16 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload16) p MemFlags Offset))
)
(decl uload16_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload16_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload16Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload16 (MemFlags Value Offset32) Inst)
(extractor
(sload16 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload16) p MemFlags Offset))
)
(decl sload16_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload16_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload16Complex) (value_list_slice args) MemFlags Offset))
)
(decl istore16 (MemFlags Value Value Offset32) Inst)
(extractor
(istore16 MemFlags x p Offset)
(inst_data (InstructionData.Store (Opcode.Istore16) (value_array_2 x p) MemFlags Offset))
)
(decl istore16_complex (MemFlags Value ValueSlice Offset32) Inst)
(extractor
(istore16_complex MemFlags x args Offset)
(inst_data (InstructionData.StoreComplex (Opcode.Istore16Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
)
(decl uload32 (MemFlags Value Offset32) Inst)
(extractor
(uload32 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload32) p MemFlags Offset))
)
(decl uload32_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload32_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload32Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload32 (MemFlags Value Offset32) Inst)
(extractor
(sload32 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload32) p MemFlags Offset))
)
(decl sload32_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload32_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload32Complex) (value_list_slice args) MemFlags Offset))
)
(decl istore32 (MemFlags Value Value Offset32) Inst)
(extractor
(istore32 MemFlags x p Offset)
(inst_data (InstructionData.Store (Opcode.Istore32) (value_array_2 x p) MemFlags Offset))
)
(decl istore32_complex (MemFlags Value ValueSlice Offset32) Inst)
(extractor
(istore32_complex MemFlags x args Offset)
(inst_data (InstructionData.StoreComplex (Opcode.Istore32Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
)
(decl uload8x8 (MemFlags Value Offset32) Inst)
(extractor
(uload8x8 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload8x8) p MemFlags Offset))
)
(decl uload8x8_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload8x8_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload8x8Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload8x8 (MemFlags Value Offset32) Inst)
(extractor
(sload8x8 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload8x8) p MemFlags Offset))
)
(decl sload8x8_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload8x8_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload8x8Complex) (value_list_slice args) MemFlags Offset))
)
(decl uload16x4 (MemFlags Value Offset32) Inst)
(extractor
(uload16x4 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload16x4) p MemFlags Offset))
)
(decl uload16x4_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload16x4_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload16x4Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload16x4 (MemFlags Value Offset32) Inst)
(extractor
(sload16x4 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload16x4) p MemFlags Offset))
)
(decl sload16x4_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload16x4_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload16x4Complex) (value_list_slice args) MemFlags Offset))
)
(decl uload32x2 (MemFlags Value Offset32) Inst)
(extractor
(uload32x2 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Uload32x2) p MemFlags Offset))
)
(decl uload32x2_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(uload32x2_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Uload32x2Complex) (value_list_slice args) MemFlags Offset))
)
(decl sload32x2 (MemFlags Value Offset32) Inst)
(extractor
(sload32x2 MemFlags p Offset)
(inst_data (InstructionData.Load (Opcode.Sload32x2) p MemFlags Offset))
)
(decl sload32x2_complex (MemFlags ValueSlice Offset32) Inst)
(extractor
(sload32x2_complex MemFlags args Offset)
(inst_data (InstructionData.LoadComplex (Opcode.Sload32x2Complex) (value_list_slice args) MemFlags Offset))
)
(decl stack_load (StackSlot Offset32) Inst)
(extractor
(stack_load SS Offset)

8
cranelift/codegen/src/ir/instructions.rs
View File

@@ -304,9 +304,7 @@ impl InstructionData {
Some(DataValue::from(imm as i32)) // Note the switch from unsigned to signed.
}
&InstructionData::Load { offset, .. }
| &InstructionData::LoadComplex { offset, .. }
| &InstructionData::Store { offset, .. }
| &InstructionData::StoreComplex { offset, .. }
| &InstructionData::StackLoad { offset, .. }
| &InstructionData::StackStore { offset, .. }
| &InstructionData::TableAddr { offset, .. } => Some(DataValue::from(offset)),
@@ -388,10 +386,8 @@ impl InstructionData {
match self {
&InstructionData::Load { offset, .. }
| &InstructionData::StackLoad { offset, .. }
| &InstructionData::LoadComplex { offset, .. }
| &InstructionData::Store { offset, .. }
| &InstructionData::StackStore { offset, .. }
| &InstructionData::StoreComplex { offset, .. } => Some(offset.into()),
| &InstructionData::StackStore { offset, .. } => Some(offset.into()),
_ => None,
}
}
@@ -400,10 +396,8 @@ impl InstructionData {
pub fn memflags(&self) -> Option<MemFlags> {
match self {
&InstructionData::Load { flags, .. }
| &InstructionData::LoadComplex { flags, .. }
| &InstructionData::LoadNoOffset { flags, .. }
| &InstructionData::Store { flags, .. }
| &InstructionData::StoreComplex { flags, .. }
| &InstructionData::StoreNoOffset { flags, .. } => Some(flags),
_ => None,
}

30
cranelift/codegen/src/isa/aarch64/lower.rs
View File

@@ -662,8 +662,8 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
roots: &[InsnInput],
offset: i32,
) -> AMode {
// TODO: support base_reg + scale * index_reg. For this, we would need to pattern-match shl or
// mul instructions (Load/StoreComplex don't include scale factors).
// TODO: support base_reg + scale * index_reg. For this, we would need to
// pattern-match shl or mul instructions.
// Collect addends through an arbitrary tree of 32-to-64-bit sign/zero
// extends and addition ops. We update these as we consume address
@@ -1510,25 +1510,13 @@ pub(crate) fn emit_atomic_load<C: LowerCtx<I = Inst>>(
fn load_op_to_ty(op: Opcode) -> Option<Type> {
match op {
Opcode::Sload8 | Opcode::Uload8 | Opcode::Sload8Complex | Opcode::Uload8Complex => Some(I8),
Opcode::Sload16 | Opcode::Uload16 | Opcode::Sload16Complex | Opcode::Uload16Complex => {
Some(I16)
}
Opcode::Sload32 | Opcode::Uload32 | Opcode::Sload32Complex | Opcode::Uload32Complex => {
Some(I32)
}
Opcode::Load | Opcode::LoadComplex => None,
Opcode::Sload8x8 | Opcode::Uload8x8 | Opcode::Sload8x8Complex | Opcode::Uload8x8Complex => {
Some(I8X8)
}
Opcode::Sload16x4
| Opcode::Uload16x4
| Opcode::Sload16x4Complex
| Opcode::Uload16x4Complex => Some(I16X4),
Opcode::Sload32x2
| Opcode::Uload32x2
| Opcode::Sload32x2Complex
| Opcode::Uload32x2Complex => Some(I32X2),
Opcode::Sload8 | Opcode::Uload8 => Some(I8),
Opcode::Sload16 | Opcode::Uload16 => Some(I16),
Opcode::Sload32 | Opcode::Uload32 => Some(I32),
Opcode::Load => None,
Opcode::Sload8x8 | Opcode::Uload8x8 => Some(I8X8),
Opcode::Sload16x4 | Opcode::Uload16x4 => Some(I16X4),
Opcode::Sload32x2 | Opcode::Uload32x2 => Some(I32X2),
_ => None,
}
}

2
cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest
View File

@@ -1,4 +1,4 @@
src/clif.isle 9ea75a6f790b5c03
src/clif.isle 443b34b797fc8ace
src/prelude.isle 74d9514ac948e163
src/isa/aarch64/inst.isle 19ccefb6a496d392
src/isa/aarch64/lower.isle d88b62dd6b40622

45
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -98,32 +98,14 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::Sload16
| Opcode::Uload32
| Opcode::Sload32
| Opcode::LoadComplex
| Opcode::Uload8Complex
| Opcode::Sload8Complex
| Opcode::Uload16Complex
| Opcode::Sload16Complex
| Opcode::Uload32Complex
| Opcode::Sload32Complex
| Opcode::Sload8x8
| Opcode::Uload8x8
| Opcode::Sload16x4
| Opcode::Uload16x4
| Opcode::Sload32x2
| Opcode::Uload32x2
| Opcode::Uload8x8Complex
| Opcode::Sload8x8Complex
| Opcode::Uload16x4Complex
| Opcode::Sload16x4Complex
| Opcode::Uload32x2Complex
| Opcode::Sload32x2Complex => {
| Opcode::Uload32x2 => {
let sign_extend = match op {
Opcode::Sload8
| Opcode::Sload8Complex
| Opcode::Sload16
| Opcode::Sload16Complex
| Opcode::Sload32
| Opcode::Sload32Complex => true,
Opcode::Sload8 | Opcode::Sload16 | Opcode::Sload32 => true,
_ => false,
};
let flags = ctx
@@ -174,17 +156,11 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let vec_extend = match op {
Opcode::Sload8x8 => Some(VecExtendOp::Sxtl8),
Opcode::Sload8x8Complex => Some(VecExtendOp::Sxtl8),
Opcode::Uload8x8 => Some(VecExtendOp::Uxtl8),
Opcode::Uload8x8Complex => Some(VecExtendOp::Uxtl8),
Opcode::Sload16x4 => Some(VecExtendOp::Sxtl16),
Opcode::Sload16x4Complex => Some(VecExtendOp::Sxtl16),
Opcode::Uload16x4 => Some(VecExtendOp::Uxtl16),
Opcode::Uload16x4Complex => Some(VecExtendOp::Uxtl16),
Opcode::Sload32x2 => Some(VecExtendOp::Sxtl32),
Opcode::Sload32x2Complex => Some(VecExtendOp::Sxtl32),
Opcode::Uload32x2 => Some(VecExtendOp::Uxtl32),
Opcode::Uload32x2Complex => Some(VecExtendOp::Uxtl32),
_ => None,
};
@@ -204,20 +180,13 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
}
Opcode::Store
| Opcode::Istore8
| Opcode::Istore16
| Opcode::Istore32
| Opcode::StoreComplex
| Opcode::Istore8Complex
| Opcode::Istore16Complex
| Opcode::Istore32Complex => {
Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
let off = ctx.data(insn).load_store_offset().unwrap();
let elem_ty = match op {
Opcode::Istore8 | Opcode::Istore8Complex => I8,
Opcode::Istore16 | Opcode::Istore16Complex => I16,
Opcode::Istore32 | Opcode::Istore32Complex => I32,
Opcode::Store | Opcode::StoreComplex => ctx.input_ty(insn, 0),
Opcode::Istore8 => I8,
Opcode::Istore16 => I16,
Opcode::Istore32 => I32,
Opcode::Store => ctx.input_ty(insn, 0),
_ => unreachable!(),
};
let is_float = ty_has_float_or_vec_representation(elem_ty);

20
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -291,17 +291,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::FminPseudo
| Opcode::FmaxPseudo
| Opcode::Uload8x8
| Opcode::Uload8x8Complex
| Opcode::Sload8x8
| Opcode::Sload8x8Complex
| Opcode::Uload16x4
| Opcode::Uload16x4Complex
| Opcode::Sload16x4
| Opcode::Sload16x4Complex
| Opcode::Uload32x2
| Opcode::Uload32x2Complex
| Opcode::Sload32x2
| Opcode::Sload32x2Complex
| Opcode::Vconst
| Opcode::Shuffle
| Opcode::Vsplit
@@ -333,20 +327,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
panic!("Unused opcode should not be encountered.");
}
Opcode::LoadComplex
| Opcode::Uload8Complex
| Opcode::Sload8Complex
| Opcode::Uload16Complex
| Opcode::Sload16Complex
| Opcode::Uload32Complex
| Opcode::Sload32Complex
| Opcode::StoreComplex
| Opcode::Istore8Complex
| Opcode::Istore16Complex
| Opcode::Istore32Complex => {
panic!("Load/store complex opcode should not be encountered.");
}
Opcode::Ifcmp
| Opcode::Ffcmp
| Opcode::Trapff

2
cranelift/codegen/src/isa/s390x/lower/isle/generated_code.manifest
View File

@@ -1,4 +1,4 @@
src/clif.isle 9ea75a6f790b5c03
src/clif.isle 443b34b797fc8ace
src/prelude.isle 74d9514ac948e163
src/isa/s390x/inst.isle d91a16074ab186a8
src/isa/s390x/lower.isle 1cc5a12adc8c75f9

126
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -2173,13 +2173,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::Sload16
| Opcode::Uload32
| Opcode::Sload32
| Opcode::LoadComplex
| Opcode::Uload8Complex
| Opcode::Sload8Complex
| Opcode::Uload16Complex
| Opcode::Sload16Complex
| Opcode::Uload32Complex
| Opcode::Sload32Complex
| Opcode::Sload8x8
| Opcode::Uload8x8
| Opcode::Sload16x4
@@ -2189,30 +2182,13 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let offset = ctx.data(insn).load_store_offset().unwrap();
let elem_ty = match op {
Opcode::Sload8 | Opcode::Uload8 | Opcode::Sload8Complex | Opcode::Uload8Complex => {
types::I8
}
Opcode::Sload16
| Opcode::Uload16
| Opcode::Sload16Complex
| Opcode::Uload16Complex => types::I16,
Opcode::Sload32
| Opcode::Uload32
| Opcode::Sload32Complex
| Opcode::Uload32Complex => types::I32,
Opcode::Sload8x8
| Opcode::Uload8x8
| Opcode::Sload8x8Complex
| Opcode::Uload8x8Complex => types::I8X8,
Opcode::Sload16x4
| Opcode::Uload16x4
| Opcode::Sload16x4Complex
| Opcode::Uload16x4Complex => types::I16X4,
Opcode::Sload32x2
| Opcode::Uload32x2
| Opcode::Sload32x2Complex
| Opcode::Uload32x2Complex => types::I32X2,
Opcode::Load | Opcode::LoadComplex => ctx.output_ty(insn, 0),
Opcode::Sload8 | Opcode::Uload8 => types::I8,
Opcode::Sload16 | Opcode::Uload16 => types::I16,
Opcode::Sload32 | Opcode::Uload32 => types::I32,
Opcode::Sload8x8 | Opcode::Uload8x8 => types::I8X8,
Opcode::Sload16x4 | Opcode::Uload16x4 => types::I16X4,
Opcode::Sload32x2 | Opcode::Uload32x2 => types::I32X2,
Opcode::Load => ctx.output_ty(insn, 0),
_ => unimplemented!(),
};
@@ -2220,17 +2196,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let sign_extend = match op {
Opcode::Sload8
| Opcode::Sload8Complex
| Opcode::Sload16
| Opcode::Sload16Complex
| Opcode::Sload32
| Opcode::Sload32Complex
| Opcode::Sload8x8
| Opcode::Sload8x8Complex
| Opcode::Sload16x4
| Opcode::Sload16x4Complex
| Opcode::Sload32x2
| Opcode::Sload32x2Complex => true,
| Opcode::Sload32x2 => true,
_ => false,
};
@@ -2251,37 +2221,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
assert_eq!(inputs.len(), 1, "only one input for load operands");
lower_to_amode(ctx, inputs[0], offset)
}
Opcode::LoadComplex
| Opcode::Uload8Complex
| Opcode::Sload8Complex
| Opcode::Uload16Complex
| Opcode::Sload16Complex
| Opcode::Uload32Complex
| Opcode::Sload32Complex
| Opcode::Sload8x8Complex
| Opcode::Uload8x8Complex
| Opcode::Sload16x4Complex
| Opcode::Uload16x4Complex
| Opcode::Sload32x2Complex
| Opcode::Uload32x2Complex => {
assert_eq!(
inputs.len(),
2,
"can't handle more than two inputs in complex load"
);
let base = put_input_in_reg(ctx, inputs[0]);
let index = put_input_in_reg(ctx, inputs[1]);
let shift = 0;
let flags = ctx.memflags(insn).expect("load should have memflags");
Amode::imm_reg_reg_shift(
offset as u32,
Gpr::new(base).unwrap(),
Gpr::new(index).unwrap(),
shift,
)
.with_flags(flags)
}
_ => unreachable!(),
};
@@ -2347,21 +2286,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
}
Opcode::Store
| Opcode::Istore8
| Opcode::Istore16
| Opcode::Istore32
| Opcode::StoreComplex
| Opcode::Istore8Complex
| Opcode::Istore16Complex
| Opcode::Istore32Complex => {
Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
let offset = ctx.data(insn).load_store_offset().unwrap();
let elem_ty = match op {
Opcode::Istore8 | Opcode::Istore8Complex => types::I8,
Opcode::Istore16 | Opcode::Istore16Complex => types::I16,
Opcode::Istore32 | Opcode::Istore32Complex => types::I32,
Opcode::Store | Opcode::StoreComplex => ctx.input_ty(insn, 0),
Opcode::Istore8 => types::I8,
Opcode::Istore16 => types::I16,
Opcode::Istore32 => types::I32,
Opcode::Store => ctx.input_ty(insn, 0),
_ => unreachable!(),
};
@@ -2370,29 +2302,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
assert_eq!(inputs.len(), 2, "only one input for store memory operands");
lower_to_amode(ctx, inputs[1], offset)
}
Opcode::StoreComplex
| Opcode::Istore8Complex
| Opcode::Istore16Complex
| Opcode::Istore32Complex => {
assert_eq!(
inputs.len(),
3,
"can't handle more than two inputs in complex store"
);
let base = put_input_in_reg(ctx, inputs[1]);
let index = put_input_in_reg(ctx, inputs[2]);
let shift = 0;
let flags = ctx.memflags(insn).expect("store should have memflags");
Amode::imm_reg_reg_shift(
offset as u32,
Gpr::new(base).unwrap(),
Gpr::new(index).unwrap(),
shift,
)
.with_flags(flags)
}
_ => unreachable!(),
};
@@ -3293,15 +3202,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
// Unimplemented opcodes below. These are not currently used by Wasm
// lowering or other known embeddings, but should be either supported or
// removed eventually.
Opcode::Uload8x8Complex
| Opcode::Sload8x8Complex
| Opcode::Uload16x4Complex
| Opcode::Sload16x4Complex
| Opcode::Uload32x2Complex
| Opcode::Sload32x2Complex => {
unimplemented!("Vector load {:?} not implemented", op);
}
Opcode::Cls => unimplemented!("Cls not supported"),
Opcode::Fma => unimplemented!("Fma not supported"),

2
cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest
View File

@@ -1,4 +1,4 @@
src/clif.isle 9ea75a6f790b5c03
src/clif.isle 443b34b797fc8ace
src/prelude.isle 74d9514ac948e163
src/isa/x64/inst.isle a002d62dcfce285
src/isa/x64/lower.isle 8f3e1ed2929fd07e

4
cranelift/codegen/src/licm.rs
View File

@@ -147,9 +147,7 @@ fn trivially_unsafe_for_licm(opcode: Opcode) -> bool {
fn is_unsafe_load(inst_data: &InstructionData) -> bool {
match *inst_data {
InstructionData::Load { flags, .. } | InstructionData::LoadComplex { flags, .. } => {
!flags.readonly() || !flags.notrap()
}
InstructionData::Load { flags, .. } => !flags.readonly() || !flags.notrap(),
_ => inst_data.opcode().can_load(),
}
}

4
cranelift/codegen/src/machinst/lower.rs
View File

@@ -1101,10 +1101,8 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
&InstructionData::AtomicCas { flags, .. } => Some(flags),
&InstructionData::AtomicRmw { flags, .. } => Some(flags),
&InstructionData::Load { flags, .. }
| &InstructionData::LoadComplex { flags, .. }
| &InstructionData::LoadNoOffset { flags, .. }
| &InstructionData::Store { flags, .. }
| &InstructionData::StoreComplex { flags, .. } => Some(flags),
| &InstructionData::Store { flags, .. } => Some(flags),
&InstructionData::StoreNoOffset { flags, .. } => Some(flags),
_ => None,
}

4
cranelift/codegen/src/simple_gvn.rs
View File

@@ -24,9 +24,7 @@ fn trivially_unsafe_for_gvn(opcode: Opcode) -> bool {
/// Test that, if the specified instruction is a load, it doesn't have the `readonly` memflag.
fn is_load_and_not_readonly(inst_data: &InstructionData) -> bool {
match *inst_data {
InstructionData::Load { flags, .. } | InstructionData::LoadComplex { flags, .. } => {
!flags.readonly()
}
InstructionData::Load { flags, .. } => !flags.readonly(),
_ => inst_data.opcode().can_load(),
}
}

10
cranelift/codegen/src/verifier/mod.rs
View File

@@ -690,13 +690,6 @@ impl<'a> Verifier<'a> {
TableAddr { table, .. } => {
self.verify_table(inst, table, errors)?;
}
LoadComplex { ref args, .. } => {
self.verify_value_list(inst, args, errors)?;
}
StoreComplex { ref args, .. } => {
self.verify_value_list(inst, args, errors)?;
}
NullAry {
opcode: Opcode::GetPinnedReg,
}
@@ -1627,8 +1620,7 @@ impl<'a> Verifier<'a> {
let inst_data = &self.func.dfg[inst];
match *inst_data {
ir::InstructionData::Store { flags, .. }
| ir::InstructionData::StoreComplex { flags, .. } => {
ir::InstructionData::Store { flags, .. } => {
if flags.readonly() {
errors.fatal((
inst,

31
cranelift/codegen/src/write.rs
View File

@@ -498,43 +498,12 @@ pub fn write_operands(w: &mut dyn Write, dfg: &DataFlowGraph, inst: Inst) -> fmt
Load {
flags, arg, offset, ..
} => write!(w, "{} {}{}", flags, arg, offset),
LoadComplex {
flags,
ref args,
offset,
..
} => {
let args = args.as_slice(pool);
write!(
w,
"{} {}{}",
flags,
DisplayValuesWithDelimiter(&args, '+'),
offset
)
}
Store {
flags,
args,
offset,
..
} => write!(w, "{} {}, {}{}", flags, args[0], args[1], offset),
StoreComplex {
flags,
ref args,
offset,
..
} => {
let args = args.as_slice(pool);
write!(
w,
"{} {}, {}{}",
flags,
args[0],
DisplayValuesWithDelimiter(&args[1..], '+'),
offset
)
}
Trap { code, .. } => write!(w, " {}", code),
CondTrap { arg, code, .. } => write!(w, " {}, {}", arg, code),
IntCondTrap {