Fix put_input_in_reg

cranelift/codegen/src/isa/aarch64/lower.rs

@@ -355,7 +355,7 @@ fn put_input_in_rse<C: LowerCtx<I = Inst>>(
             && ((narrow_mode.is_32bit() && out_bits < 32)
                 || (!narrow_mode.is_32bit() && out_bits < 64))
         {
-            let reg = put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None);
+            let reg = put_input_in_reg(ctx, input, NarrowValueMode::None);
             let extendop = match (narrow_mode, out_bits) {
                 (NarrowValueMode::SignExtend32, 1) | (NarrowValueMode::SignExtend64, 1) => {
                     ExtendOp::SXTB
@@ -400,7 +400,7 @@ fn put_input_in_rse<C: LowerCtx<I = Inst>>(
                 (false, 32) => ExtendOp::UXTW,
                 _ => unreachable!(),
             };
-            let reg = put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None);
+            let reg = put_input_in_reg(ctx, input, NarrowValueMode::None);
             return ResultRSE::RegExtend(reg, extendop);
         }
     }

cranelift/filetests/filetests/vcode/aarch64/extend-op.clif

@@ -11,6 +11,7 @@ block0(v0: i8):
 
 ; check:  stp fp, lr, [sp, #-16]!
 ; nextln:  mov fp, sp
+; nextln:  sxtb x0, w0
 ; nextln:  movz x1, #42
 ; nextln:  add x0, x1, x0, SXTB
 ; nextln:  mov sp, fp

cranelift/filetests/filetests/vcode/aarch64/heap_addr.clif

@@ -20,7 +20,8 @@ block0(v0: i64, v1: i32):
 ; nextln: subs wzr, w1, w2
 ; nextln: b.ls label1 ; b label2
 ; check: Block 1:
-; check: add x0, x0, x1, UXTW
+; check: mov w3, w1
+; check: add x0, x0, x3, UXTW
 ; nextln: subs wzr, w1, w2
 ; nextln: movz x1, #0
 ; nextln: csel x0, x1, x0, hi
@@ -45,7 +46,8 @@ block0(v0: i64, v1: i32):
 ; nextln: subs wzr, w1, #65536
 ; nextln: b.ls label1 ; b label2
 ; check: Block 1:
-; check: add x0, x0, x1, UXTW
+; check: mov w2, w1
+; check: add x0, x0, x2, UXTW
 ; nextln: subs wzr, w1, #65536
 ; nextln: movz x1, #0
 ; nextln: csel x0, x1, x0, hi

cranelift/filetests/filetests/vcode/aarch64/iconst-icmp-small.clif

@@ -0,0 +1,32 @@
+; Test that `put_input_in_rse` doesn't try to put the input of the `iconst` into a register, which
+; would result in an out-of-bounds panic. (#2147)
+
+test compile
+target aarch64
+
+function u0:0() -> i8 system_v {
+
+block0:
+    v0 = iconst.i16 0xddcc
+    v1 = icmp.i16 ne v0, v0
+    v2 = bint.i8 v1
+    return v2
+}
+
+; check: VCode_ShowWithRRU {{
+; nextln: Entry block: 0
+; nextln: Block 0:
+; nextln:   (original IR block: block0)
+; nextln:   (instruction range: 0 .. 11)
+; nextln:   Inst 0:   stp fp, lr, [sp, #-16]!
+; nextln:   Inst 1:   mov fp, sp
+; nextln:   Inst 2:   movz x0, #56780
+; nextln:   Inst 3:   uxth w0, w0
+; nextln:   Inst 4:   movz x1, #56780
+; nextln:   Inst 5:   subs wzr, w0, w1, UXTH
+; nextln:   Inst 6:   cset x0, ne
+; nextln:   Inst 7:   and w0, w0, #1
+; nextln:   Inst 8:   mov sp, fp
+; nextln:   Inst 9:   ldp fp, lr, [sp], #16
+; nextln:   Inst 10:   ret
+; nextln: }}

cranelift/filetests/filetests/vcode/aarch64/narrow-arithmetic.clif

@@ -49,6 +49,7 @@ block0(v0: i32, v1: i8):
 
 ; check: stp fp, lr, [sp, #-16]!
 ; nextln: mov fp, sp
+; nextln: sxtb w1, w1
 ; nextln: add w0, w0, w1, SXTB
 ; nextln: mov sp, fp
 ; nextln: ldp fp, lr, [sp], #16
@@ -63,6 +64,7 @@ block0(v0: i64, v1: i32):
 
 ; check: stp fp, lr, [sp, #-16]!
 ; nextln: mov fp, sp
+; nextln: sxtw x1, w1
 ; nextln: add x0, x0, x1, SXTW
 ; nextln: mov sp, fp
 ; nextln: ldp fp, lr, [sp], #16