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Remove the "has_sse2" flag.

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Cretonne currently requires SSE2 support pervasively, so it's not meaningful
to have a setting for it.
This commit is contained in:
Dan Gohman
2018-03-12 10:28:19 -07:00
parent e441337e4b
commit b8a106adf0
2 changed files with 10 additions and 12 deletions
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7
lib/cretonne/meta/isa/intel/settings.py
View File

@@ -11,9 +11,6 @@ ISA.settings = SettingGroup('intel', parent=shared.group)
# The has_* settings here correspond to CPUID bits. # The has_* settings here correspond to CPUID bits.
# CPUID.01H:EDX
has_sse2 = BoolSetting("SSE2: CPUID.01H:EDX.SSE2[bit 26]")
# CPUID.01H:ECX # CPUID.01H:ECX
has_sse3 = BoolSetting("SSE3: CPUID.01H:ECX.SSE3[bit 0]") has_sse3 = BoolSetting("SSE3: CPUID.01H:ECX.SSE3[bit 0]")
has_ssse3 = BoolSetting("SSSE3: CPUID.01H:ECX.SSSE3[bit 9]") has_ssse3 = BoolSetting("SSSE3: CPUID.01H:ECX.SSSE3[bit 9]")
@@ -40,9 +37,9 @@ use_lzcnt = And(has_lzcnt)
# Presets corresponding to Intel CPUs. # Presets corresponding to Intel CPUs.
baseline = Preset(has_sse2) baseline = Preset()
nehalem = Preset( nehalem = Preset(
has_sse2, has_sse3, has_ssse3, has_sse41, has_sse42, has_popcnt) has_sse3, has_ssse3, has_sse41, has_sse42, has_popcnt)
haswell = Preset(nehalem, has_bmi1, has_lzcnt) haswell = Preset(nehalem, has_bmi1, has_lzcnt)
ISA.settings.close(globals()) ISA.settings.close(globals())

15
lib/native/src/lib.rs
View File

@@ -19,7 +19,7 @@ use raw_cpuid::CpuId;
/// Return `settings` and `isa` builders configured for the current host /// Return `settings` and `isa` builders configured for the current host
/// machine, or `Err(())` if the host machine is not supported /// machine, or `Err(())` if the host machine is not supported
/// in the current configuration. /// in the current configuration.
pub fn builders() -> Result<(settings::Builder, isa::Builder), ()> { pub fn builders() -> Result<(settings::Builder, isa::Builder), &'static str> {
let mut flag_builder = settings::builder(); let mut flag_builder = settings::builder();
// TODO: Add RISC-V support once Rust supports it. // TODO: Add RISC-V support once Rust supports it.
@@ -35,28 +35,28 @@ pub fn builders() -> Result<(settings::Builder, isa::Builder), ()> {
} else if cfg!(target_arch = "aarch64") { } else if cfg!(target_arch = "aarch64") {
"arm64" "arm64"
} else { } else {
return Err(()); return Err("unrecognized architecture");
}; };
let mut isa_builder = isa::lookup(name).map_err(|err| match err { let mut isa_builder = isa::lookup(name).map_err(|err| match err {
isa::LookupError::Unknown => panic!(), isa::LookupError::Unknown => panic!(),
isa::LookupError::Unsupported => (), isa::LookupError::Unsupported => "unsupported architecture",
})?; })?;
if cfg!(any(target_arch = "x86", target_arch = "x86_64")) { if cfg!(any(target_arch = "x86", target_arch = "x86_64")) {
parse_x86_cpuid(&mut isa_builder); parse_x86_cpuid(&mut isa_builder)?;
} }
Ok((flag_builder, isa_builder)) Ok((flag_builder, isa_builder))
} }
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
fn parse_x86_cpuid(isa_builder: &mut isa::Builder) { fn parse_x86_cpuid(isa_builder: &mut isa::Builder) -> Result<(), &'static str> {
let cpuid = CpuId::new(); let cpuid = CpuId::new();
if let Some(info) = cpuid.get_feature_info() { if let Some(info) = cpuid.get_feature_info() {
if info.has_sse2() { if !info.has_sse2() {
isa_builder.enable("has_sse2").unwrap(); return Err("x86 support requires SSE2");
} }
if info.has_sse3() { if info.has_sse3() {
isa_builder.enable("has_sse3").unwrap(); isa_builder.enable("has_sse3").unwrap();
@@ -87,4 +87,5 @@ fn parse_x86_cpuid(isa_builder: &mut isa::Builder) {
isa_builder.enable("has_lzcnt").unwrap(); isa_builder.enable("has_lzcnt").unwrap();
} }
} }
Ok(())
} }