diff --git a/lib/cretonne/meta/isa/intel/settings.py b/lib/cretonne/meta/isa/intel/settings.py
index 5817c48c0e..c62012e0c1 100644
--- a/lib/cretonne/meta/isa/intel/settings.py
+++ b/lib/cretonne/meta/isa/intel/settings.py
@@ -11,9 +11,6 @@ ISA.settings = SettingGroup('intel', parent=shared.group)
 
 # The has_* settings here correspond to CPUID bits.
 
-# CPUID.01H:EDX
-has_sse2 = BoolSetting("SSE2: CPUID.01H:EDX.SSE2[bit 26]")
-
 # CPUID.01H:ECX
 has_sse3 = BoolSetting("SSE3: CPUID.01H:ECX.SSE3[bit 0]")
 has_ssse3 = BoolSetting("SSSE3: CPUID.01H:ECX.SSSE3[bit 9]")
@@ -40,9 +37,9 @@ use_lzcnt = And(has_lzcnt)
 
 # Presets corresponding to Intel CPUs.
 
-baseline = Preset(has_sse2)
+baseline = Preset()
 nehalem = Preset(
-        has_sse2, has_sse3, has_ssse3, has_sse41, has_sse42, has_popcnt)
+        has_sse3, has_ssse3, has_sse41, has_sse42, has_popcnt)
 haswell = Preset(nehalem, has_bmi1, has_lzcnt)
 
 ISA.settings.close(globals())
diff --git a/lib/native/src/lib.rs b/lib/native/src/lib.rs
index d7c6a8d0ab..ea828ea252 100644
--- a/lib/native/src/lib.rs
+++ b/lib/native/src/lib.rs
@@ -19,7 +19,7 @@ use raw_cpuid::CpuId;
 /// Return `settings` and `isa` builders configured for the current host
 /// machine, or `Err(())` if the host machine is not supported
 /// in the current configuration.
-pub fn builders() -> Result<(settings::Builder, isa::Builder), ()> {
+pub fn builders() -> Result<(settings::Builder, isa::Builder), &'static str> {
     let mut flag_builder = settings::builder();
 
     // TODO: Add RISC-V support once Rust supports it.
@@ -35,28 +35,28 @@ pub fn builders() -> Result<(settings::Builder, isa::Builder), ()> {
     } else if cfg!(target_arch = "aarch64") {
         "arm64"
     } else {
-        return Err(());
+        return Err("unrecognized architecture");
     };
 
     let mut isa_builder = isa::lookup(name).map_err(|err| match err {
         isa::LookupError::Unknown => panic!(),
-        isa::LookupError::Unsupported => (),
+        isa::LookupError::Unsupported => "unsupported architecture",
     })?;
 
     if cfg!(any(target_arch = "x86", target_arch = "x86_64")) {
-        parse_x86_cpuid(&mut isa_builder);
+        parse_x86_cpuid(&mut isa_builder)?;
     }
 
     Ok((flag_builder, isa_builder))
 }
 
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-fn parse_x86_cpuid(isa_builder: &mut isa::Builder) {
+fn parse_x86_cpuid(isa_builder: &mut isa::Builder) -> Result<(), &'static str> {
     let cpuid = CpuId::new();
 
     if let Some(info) = cpuid.get_feature_info() {
-        if info.has_sse2() {
-            isa_builder.enable("has_sse2").unwrap();
+        if !info.has_sse2() {
+            return Err("x86 support requires SSE2");
         }
         if info.has_sse3() {
             isa_builder.enable("has_sse3").unwrap();
@@ -87,4 +87,5 @@ fn parse_x86_cpuid(isa_builder: &mut isa::Builder) {
             isa_builder.enable("has_lzcnt").unwrap();
         }
     }
+    Ok(())
 }