Generate SSA code from returns (#5172)

Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.

cranelift/filetests/filetests/isa/aarch64/floating-point.clif

@@ -309,8 +309,8 @@ block0(v0: f32, v1: f32):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   ushr v4.2s, v1.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f32(f64, f64) -> f64 {
@@ -320,8 +320,8 @@ block0(v0: f64, v1: f64):
 }
 
 ; block0:
-;   ushr d5, d1, #63
-;   sli d0, d0, d5, #63
+;   ushr d4, d1, #63
+;   sli d0, d0, d4, #63
 ;   ret
 
 function %f33(f32) -> i32 {
@@ -333,12 +333,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #20352, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #20352, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, s0
 ;   ret
@@ -352,13 +352,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #52992, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #52992, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #20224, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #20224, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, s0
 ;   ret
@@ -372,12 +372,12 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   fmov s5, #-1
-;   fcmp s0, s5
+;   fmov s4, #-1
+;   fcmp s0, s4
 ;   b.gt 8 ; udf
-;   movz x10, #24448, LSL #16
-;   fmov s18, w10
-;   fcmp s0, s18
+;   movz x9, #24448, LSL #16
+;   fmov s17, w9
+;   fcmp s0, s17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, s0
 ;   ret
@@ -391,13 +391,13 @@ block0(v0: f32):
 ; block0:
 ;   fcmp s0, s0
 ;   b.vc 8 ; udf
-;   movz x6, #57088, LSL #16
-;   fmov s6, w6
-;   fcmp s0, s6
+;   movz x5, #57088, LSL #16
+;   fmov s5, w5
+;   fcmp s0, s5
 ;   b.ge 8 ; udf
-;   movz x12, #24320, LSL #16
-;   fmov s20, w12
-;   fcmp s0, s20
+;   movz x11, #24320, LSL #16
+;   fmov s19, w11
+;   fcmp s0, s19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, s0
 ;   ret
@@ -411,12 +411,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16880, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16880, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu w0, d0
 ;   ret
@@ -430,12 +430,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   ldr d5, pc+8 ; b 12 ; data.f64 -2147483649
-;   fcmp d0, d5
+;   ldr d4, pc+8 ; b 12 ; data.f64 -2147483649
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #16864, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #16864, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzs w0, d0
 ;   ret
@@ -449,12 +449,12 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   fmov d5, #-1
-;   fcmp d0, d5
+;   fmov d4, #-1
+;   fcmp d0, d4
 ;   b.gt 8 ; udf
-;   movz x10, #17392, LSL #48
-;   fmov d18, x10
-;   fcmp d0, d18
+;   movz x9, #17392, LSL #48
+;   fmov d17, x9
+;   fcmp d0, d17
 ;   b.lt 8 ; udf
 ;   fcvtzu x0, d0
 ;   ret
@@ -468,13 +468,13 @@ block0(v0: f64):
 ; block0:
 ;   fcmp d0, d0
 ;   b.vc 8 ; udf
-;   movz x6, #50144, LSL #48
-;   fmov d6, x6
-;   fcmp d0, d6
+;   movz x5, #50144, LSL #48
+;   fmov d5, x5
+;   fcmp d0, d5
 ;   b.ge 8 ; udf
-;   movz x12, #17376, LSL #48
-;   fmov d20, x12
-;   fcmp d0, d20
+;   movz x11, #17376, LSL #48
+;   fmov d19, x11
+;   fcmp d0, d19
 ;   b.lt 8 ; udf
 ;   fcvtzs x0, d0
 ;   ret
@@ -776,9 +776,9 @@ block0(v0: f32x4, v1: f32x4, v2: f32x4):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.4s, v5.4s, v0.4s, v1.4s
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.4s, v0.4s, v5.4s, v1.4s
 ;   ret
 
 function %f71(f32x2, f32x2, f32x2) -> f32x2 {
@@ -788,9 +788,9 @@ block0(v0: f32x2, v1: f32x2, v2: f32x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.2s, v5.2s, v0.2s, v1.2s
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2s, v0.2s, v5.2s, v1.2s
 ;   ret
 
 function %f72(f64x2, f64x2, f64x2) -> f64x2 {
@@ -800,9 +800,9 @@ block0(v0: f64x2, v1: f64x2, v2: f64x2):
 }
 
 ; block0:
-;   mov v5.16b, v2.16b
-;   fmla v5.2d, v5.2d, v0.2d, v1.2d
-;   mov v0.16b, v5.16b
+;   mov v5.16b, v0.16b
+;   mov v0.16b, v2.16b
+;   fmla v0.2d, v0.2d, v5.2d, v1.2d
 ;   ret
 
 function %f73(f32x2, f32x2) -> f32x2 {
@@ -812,8 +812,8 @@ block0(v0: f32x2, v1: f32x2):
 }
 
 ; block0:
-;   ushr v5.2s, v1.2s, #31
-;   sli v0.2s, v0.2s, v5.2s, #31
+;   ushr v4.2s, v1.2s, #31
+;   sli v0.2s, v0.2s, v4.2s, #31
 ;   ret
 
 function %f74(f32x4, f32x4) -> f32x4 {
@@ -823,8 +823,8 @@ block0(v0: f32x4, v1: f32x4):
 }
 
 ; block0:
-;   ushr v5.4s, v1.4s, #31
-;   sli v0.4s, v0.4s, v5.4s, #31
+;   ushr v4.4s, v1.4s, #31
+;   sli v0.4s, v0.4s, v4.4s, #31
 ;   ret
 
 function %f75(f64x2, f64x2) -> f64x2 {
@@ -834,6 +834,7 @@ block0(v0: f64x2, v1: f64x2):
 }
 
 ; block0:
-;   ushr v5.2d, v1.2d, #63
-;   sli v0.2d, v0.2d, v5.2d, #63
+;   ushr v4.2d, v1.2d, #63
+;   sli v0.2d, v0.2d, v4.2d, #63
 ;   ret
+