Generate SSA code from returns (#5172)
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
This commit is contained in:
Trevor Elliott
@@ -136,6 +136,17 @@ pub struct ArgPair {
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pub preg: Reg,
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}
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/// A type used by backends to track return register binding info in the "ret"
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/// pseudoinst. The pseudoinst holds a vec of `RetPair` structs.
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#[derive(Clone, Debug)]
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pub struct RetPair {
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/// The vreg that is returned by this pseudionst.
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pub vreg: Reg,
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/// The preg that the arg is returned through; this constrains the vreg's
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/// placement at the pseudoinst.
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pub preg: Reg,
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}
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/// A location for (part of) an argument or return value. These "storage slots"
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/// are specified for each register-sized part of an argument.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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@@ -421,7 +432,7 @@ pub trait ABIMachineSpec {
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fn gen_args(isa_flags: &Self::F, args: Vec<ArgPair>) -> Self::I;
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/// Generate a return instruction.
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fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec<Reg>) -> Self::I;
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fn gen_ret(setup_frame: bool, isa_flags: &Self::F, rets: Vec<RetPair>) -> Self::I;
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/// Generate an add-with-immediate. Note that even if this uses a scratch
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/// register, it must satisfy two requirements:
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@@ -1483,8 +1494,10 @@ impl<M: ABIMachineSpec> Callee<M> {
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&self,
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sigs: &SigSet,
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idx: usize,
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from_regs: ValueRegs<Writable<Reg>>,
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) -> SmallInstVec<M::I> {
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from_regs: ValueRegs<Reg>,
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vregs: &mut VRegAllocator<M::I>,
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) -> (SmallVec<[RetPair; 2]>, SmallInstVec<M::I>) {
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let mut reg_pairs = smallvec![];
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let mut ret = smallvec![];
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let word_bits = M::word_bits() as u8;
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match &sigs[self.sig].rets(sigs)[idx] {
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@@ -1497,24 +1510,31 @@ impl<M: ABIMachineSpec> Callee<M> {
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} => {
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let from_bits = ty_bits(ty) as u8;
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let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension);
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let reg: Writable<Reg> = Writable::from_reg(Reg::from(reg));
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match (ext, from_bits) {
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(ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
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let vreg = match (ext, from_bits) {
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(ir::ArgumentExtension::Uext, n)
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| (ir::ArgumentExtension::Sext, n)
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if n < word_bits =>
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{
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let signed = ext == ArgumentExtension::Sext;
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let signed = ext == ir::ArgumentExtension::Sext;
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let dst = writable_value_regs(vregs.alloc(ty).unwrap())
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.only_reg()
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.unwrap();
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ret.push(M::gen_extend(
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reg,
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from_reg.to_reg(),
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signed,
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from_bits,
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dst, from_reg, signed, from_bits,
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/* to_bits = */ word_bits,
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));
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dst.to_reg()
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}
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_ => {
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ret.push(M::gen_move(reg, from_reg.to_reg(), ty));
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// No move needed, regalloc2 will emit it using the constraint
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// added by the RetPair.
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from_reg
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}
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};
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reg_pairs.push(RetPair {
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vreg,
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preg: Reg::from(reg),
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});
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}
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&ABIArgSlot::Stack {
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offset,
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@@ -1533,16 +1553,17 @@ impl<M: ABIMachineSpec> Callee<M> {
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let ext = M::get_ext_mode(sigs[self.sig].call_conv, extension);
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// Trash the from_reg; it should be its last use.
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match (ext, from_bits) {
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(ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
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(ir::ArgumentExtension::Uext, n)
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| (ir::ArgumentExtension::Sext, n)
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if n < word_bits =>
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{
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assert_eq!(M::word_reg_class(), from_reg.to_reg().class());
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let signed = ext == ArgumentExtension::Sext;
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assert_eq!(M::word_reg_class(), from_reg.class());
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let signed = ext == ir::ArgumentExtension::Sext;
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let dst = writable_value_regs(vregs.alloc(ty).unwrap())
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.only_reg()
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.unwrap();
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ret.push(M::gen_extend(
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Writable::from_reg(from_reg.to_reg()),
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from_reg.to_reg(),
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signed,
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from_bits,
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dst, from_reg, signed, from_bits,
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/* to_bits = */ word_bits,
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));
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// Store the extended version.
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@@ -1553,21 +1574,21 @@ impl<M: ABIMachineSpec> Callee<M> {
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ret.push(M::gen_store_base_offset(
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self.ret_area_ptr.unwrap().to_reg(),
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off,
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from_reg.to_reg(),
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from_reg,
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ty,
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));
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}
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}
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}
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}
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&ABIArg::StructArg { .. } => {
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ABIArg::StructArg { .. } => {
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panic!("StructArg in return position is unsupported");
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}
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&ABIArg::ImplicitPtrArg { .. } => {
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ABIArg::ImplicitPtrArg { .. } => {
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panic!("ImplicitPtrArg in return position is unsupported");
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}
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}
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ret
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(reg_pairs, ret)
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}
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/// Generate any setup instruction needed to save values to the
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@@ -1594,22 +1615,7 @@ impl<M: ABIMachineSpec> Callee<M> {
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}
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/// Generate a return instruction.
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pub fn gen_ret(&self, sigs: &SigSet) -> M::I {
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let mut rets = vec![];
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for ret in sigs[self.sig].rets(sigs) {
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match ret {
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ABIArg::Slots { slots, .. } => {
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for slot in slots {
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match slot {
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ABIArgSlot::Reg { reg, .. } => rets.push(Reg::from(*reg)),
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_ => {}
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}
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}
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}
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_ => {}
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}
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}
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pub fn gen_ret(&self, rets: Vec<RetPair>) -> M::I {
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M::gen_ret(self.setup_frame, &self.isa_flags, rets)
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}
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