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Generate SSA code from returns (#5172)

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Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
This commit is contained in:
Trevor Elliott
2022-11-08 16:00:49 -08:00
committed by GitHub
parent d59caf39b6
commit b077854b57
171 changed files with 6368 additions and 6364 deletions
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2
cranelift/codegen/src/isa/riscv64/abi.rs
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@@ -235,7 +235,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
Inst::Args { args }
}
fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec<Reg>) -> Inst {
fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec<RetPair>) -> Inst {
Inst::Ret { rets }
}

2
cranelift/codegen/src/isa/riscv64/inst.isle
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@@ -71,7 +71,7 @@
(Args
(args VecArgPair))
(Ret (rets VecReg))
(Ret (rets VecRetPair))
(Extend
(rd WritableReg)

4
cranelift/codegen/src/isa/riscv64/inst/mod.rs
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@@ -352,7 +352,9 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
}
}
&Inst::Ret { ref rets } => {
collector.reg_uses(&rets[..]);
for ret in rets {
collector.reg_fixed_use(ret.vreg, ret.preg);
}
}
&Inst::Extend { rd, rn, .. } => {

15
cranelift/codegen/src/isa/riscv64/mod.rs
View File

@@ -233,13 +233,18 @@ mod test {
);
let buffer = backend.compile_function(&mut func, true).unwrap();
let code = buffer.buffer.data();
// 0: 000015b7 lui a1,0x1
// 4: 23458593 addi a1,a1,564 # 0x1234
// 8: 00b5053b addw a0,a0,a1
// To update this comment, write the golden bytes to a file, and run the following command
// on it to update:
// > riscv64-linux-gnu-objdump -b binary -D <file> -m riscv
//
// 0: 000013b7 lui t2,0x1
// 4: 23438393 addi t2,t2,564 # 0x1234
// 8: 0075053b .4byte 0x75053b
// c: 00008067 ret
let golden = vec![
0xb7, 0x15, 0x0, 0x0, 0x93, 0x85, 0x45, 0x23, 0x3b, 0x5, 0xb5, 0x0, 0x67, 0x80, 0x0,
0x0,
183, 19, 0, 0, 147, 131, 67, 35, 59, 5, 117, 0, 103, 128, 0, 0,
];
assert_eq!(code, &golden[..]);
}