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Add Intel regmove encodings.

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Same as a register copy, but different arguments.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-12 10:22:43 -07:00
parent 69f974ba5d
commit ad76f80127
2 changed files with 14 additions and 1 deletions
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6
lib/cretonne/meta/isa/intel/encodings.py
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@@ -23,11 +23,15 @@ for inst, opc in [
I64.enc(inst.i32, *r.rr(opc)) I64.enc(inst.i32, *r.rr(opc))
I32.enc(base.copy.i32, *r.ur(0x89)) I32.enc(base.copy.i32, *r.ur(0x89))
I64.enc(base.copy.i64, *r.ur.rex(0x89, w=1)) I64.enc(base.copy.i64, *r.ur.rex(0x89, w=1))
I64.enc(base.copy.i32, *r.ur.rex(0x89)) I64.enc(base.copy.i32, *r.ur.rex(0x89))
I64.enc(base.copy.i32, *r.ur(0x89)) I64.enc(base.copy.i32, *r.ur(0x89))
I32.enc(base.regmove.i32, *r.rmov(0x89))
I64.enc(base.regmove.i64, *r.rmov.rex(0x89, w=1))
I64.enc(base.regmove.i32, *r.rmov.rex(0x89))
I64.enc(base.regmove.i32, *r.rmov(0x89))
# Immediate instructions with sign-extended 8-bit and 32-bit immediate. # Immediate instructions with sign-extended 8-bit and 32-bit immediate.
for inst, rrr in [ for inst, rrr in [
(base.iadd_imm, 0), (base.iadd_imm, 0),

9
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -6,6 +6,7 @@ from cdsl.isa import EncRecipe
from cdsl.predicates import IsSignedInt, IsEqual from cdsl.predicates import IsSignedInt, IsEqual
from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
from base.formats import Call, IndirectCall, Store, Load from base.formats import Call, IndirectCall, Store, Load
from base.formats import RegMove
from .registers import GPR, ABCD from .registers import GPR, ABCD
try: try:
@@ -205,6 +206,14 @@ ur = TailRecipe(
modrm_rr(out_reg0, in_reg0, sink); modrm_rr(out_reg0, in_reg0, sink);
''') ''')
# XX /r, for regmove instructions.
rmov = TailRecipe(
'ur', RegMove, size=1, ins=GPR, outs=(),
emit='''
PUT_OP(bits, rex2(dst, src), sink);
modrm_rr(dst, src, sink);
''')
# XX /n with one arg in %rcx, for shifts. # XX /n with one arg in %rcx, for shifts.
rc = TailRecipe( rc = TailRecipe(
'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0, 'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,