From ad76f801271af81b4953c1bcd8af9e04a7ab4757 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 12 Jul 2017 10:22:43 -0700 Subject: [PATCH] Add Intel regmove encodings. Same as a register copy, but different arguments. --- lib/cretonne/meta/isa/intel/encodings.py | 6 +++++- lib/cretonne/meta/isa/intel/recipes.py | 9 +++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py index 74dd5b5999..ab32e77303 100644 --- a/lib/cretonne/meta/isa/intel/encodings.py +++ b/lib/cretonne/meta/isa/intel/encodings.py @@ -23,11 +23,15 @@ for inst, opc in [ I64.enc(inst.i32, *r.rr(opc)) I32.enc(base.copy.i32, *r.ur(0x89)) - I64.enc(base.copy.i64, *r.ur.rex(0x89, w=1)) I64.enc(base.copy.i32, *r.ur.rex(0x89)) I64.enc(base.copy.i32, *r.ur(0x89)) +I32.enc(base.regmove.i32, *r.rmov(0x89)) +I64.enc(base.regmove.i64, *r.rmov.rex(0x89, w=1)) +I64.enc(base.regmove.i32, *r.rmov.rex(0x89)) +I64.enc(base.regmove.i32, *r.rmov(0x89)) + # Immediate instructions with sign-extended 8-bit and 32-bit immediate. for inst, rrr in [ (base.iadd_imm, 0), diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 2d1fc62d80..c6c7b3f2af 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -6,6 +6,7 @@ from cdsl.isa import EncRecipe from cdsl.predicates import IsSignedInt, IsEqual from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry from base.formats import Call, IndirectCall, Store, Load +from base.formats import RegMove from .registers import GPR, ABCD try: @@ -205,6 +206,14 @@ ur = TailRecipe( modrm_rr(out_reg0, in_reg0, sink); ''') +# XX /r, for regmove instructions. +rmov = TailRecipe( + 'ur', RegMove, size=1, ins=GPR, outs=(), + emit=''' + PUT_OP(bits, rex2(dst, src), sink); + modrm_rr(dst, src, sink); + ''') + # XX /n with one arg in %rcx, for shifts. rc = TailRecipe( 'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,