Add Intel regmove encodings.

Same as a register copy, but different arguments.

lib/cretonne/meta/isa/intel/recipes.py

@@ -6,6 +6,7 @@ from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
 from base.formats import Call, IndirectCall, Store, Load
+from base.formats import RegMove
 from .registers import GPR, ABCD
 
 try:
@@ -205,6 +206,14 @@ ur = TailRecipe(
         modrm_rr(out_reg0, in_reg0, sink);
         ''')
 
+# XX /r, for regmove instructions.
+rmov = TailRecipe(
+        'ur', RegMove, size=1, ins=GPR, outs=(),
+        emit='''
+        PUT_OP(bits, rex2(dst, src), sink);
+        modrm_rr(dst, src, sink);
+        ''')
+
 # XX /n with one arg in %rcx, for shifts.
 rc = TailRecipe(
         'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,