Add an Intel-specific x86_cvtt2si instruction.

This is used to represent the non-trapping semantics of the cvttss2si and
cvttsd2si instructions (and their vectorized counterparts).

The overflow behavior of this instruction is specific to the Intel ISAs.

There is no float-to-i64 instruction on the 32-bit Intel ISA.

lib/cretonne/meta/isa/intel/recipes.py

@@ -290,6 +290,14 @@ frurm = TailRecipe(
         modrm_rr(in_reg0, out_reg0, sink);
         ''')
 
+# XX /r, RM form, FPR -> GPR.
+rfurm = TailRecipe(
+        'rfurm', Unary, size=1, ins=FPR, outs=GPR,
+        emit='''
+        PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
+        modrm_rr(in_reg0, out_reg0, sink);
+        ''')
+
 # XX /r, RMI form for one of the roundXX SSE 4.1 instructions.
 furmi_rnd = TailRecipe(
         'furmi_rnd', Unary, size=2, ins=FPR, outs=FPR,