ac69f3bfdf
This is used to represent the non-trapping semantics of the cvttss2si and cvttsd2si instructions (and their vectorized counterparts). The overflow behavior of this instruction is specific to the Intel ISAs. There is no float-to-i64 instruction on the 32-bit Intel ISA.
777 lines
25 KiB
Python
777 lines
25 KiB
Python
"""
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Intel Encoding recipes.
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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from cdsl.predicates import IsSignedInt, IsEqual, Or
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from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
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from base.formats import Trap, Call, IndirectCall, Store, Load
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from base.formats import IntCompare, FloatCompare
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from base.formats import RegMove, Ternary, Jump, Branch, FuncAddr
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from .registers import GPR, ABCD, FPR, GPR8, FPR8, StackGPR32, StackFPR32
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from .defs import supported_floatccs
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try:
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from typing import Tuple, Dict, Sequence # noqa
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from cdsl.instructions import InstructionFormat # noqa
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from cdsl.isa import ConstraintSeq, BranchRange, PredNode, OperandConstraint # noqa
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except ImportError:
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pass
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# Opcode representation.
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#
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# Cretonne requires each recipe to have a single encoding size in bytes, and
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# Intel opcodes are variable length, so we use separate recipes for different
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# styles of opcodes and prefixes. The opcode format is indicated by the recipe
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# name prefix:
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OPCODE_PREFIX = {
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# Prefix bytes Name mmpp
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(): ('Op1', 0b0000),
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(0x66,): ('Mp1', 0b0001),
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(0xf3,): ('Mp1', 0b0010),
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(0xf2,): ('Mp1', 0b0011),
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(0x0f,): ('Op2', 0b0100),
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(0x66, 0x0f): ('Mp2', 0b0101),
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(0xf3, 0x0f): ('Mp2', 0b0110),
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(0xf2, 0x0f): ('Mp2', 0b0111),
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(0x0f, 0x38): ('Op3', 0b1000),
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(0x66, 0x0f, 0x38): ('Mp3', 0b1001),
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(0xf3, 0x0f, 0x38): ('Mp3', 0b1010),
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(0xf2, 0x0f, 0x38): ('Mp3', 0b1011),
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(0x0f, 0x3a): ('Op3', 0b1100),
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(0x66, 0x0f, 0x3a): ('Mp3', 0b1101),
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(0xf3, 0x0f, 0x3a): ('Mp3', 0b1110),
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(0xf2, 0x0f, 0x3a): ('Mp3', 0b1111)
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}
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# The table above does not include the REX prefix which goes after the
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# mandatory prefix. VEX/XOP and EVEX prefixes are not yet supported. Encodings
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# using any of these prefixes are represented by separate recipes.
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#
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# The encoding bits are:
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#
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# 0-7: The opcode byte <op>.
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# 8-9: pp, mandatory prefix:
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# 00 none (Op*)
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# 01 66 (Mp*)
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# 10 F3 (Mp*)
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# 11 F2 (Mp*)
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# 10-11: mm, opcode map:
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# 00 <op> (Op1/Mp1)
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# 01 0F <op> (Op2/Mp2)
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# 10 0F 38 <op> (Op3/Mp3)
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# 11 0F 3A <op> (Op3/Mp3)
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# 12-14 rrr, opcode bits for the ModR/M byte for certain opcodes.
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# 15: REX.W bit (or VEX.W/E)
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#
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# There is some redundancy between bits 8-11 and the recipe names, but we have
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# enough bits, and the pp+mm format is ready for supporting VEX prefixes.
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def decode_ops(ops, rrr=0, w=0):
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# type: (Tuple[int, ...], int, int) -> Tuple[str, int]
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"""
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Given a sequence of opcode bytes, compute the recipe name prefix and
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encoding bits.
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"""
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assert rrr <= 0b111
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assert w <= 1
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name, mmpp = OPCODE_PREFIX[ops[:-1]]
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op = ops[-1]
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assert op <= 256
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return (name, op | (mmpp << 8) | (rrr << 12) | (w << 15))
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def replace_put_op(emit, prefix):
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# type: (str, str) -> str
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"""
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Given a snippet of Rust code (or None), replace the `PUT_OP` macro with the
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corresponding `put_*` function from the `binemit.rs` module.
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"""
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if emit is None:
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return None
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else:
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return emit.replace('PUT_OP', 'put_' + prefix.lower())
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def map_regs(
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regs, # type: Sequence[OperandConstraint]
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from_class, # type: OperandConstraint
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to_class # type: OperandConstraint
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):
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# type: (...) -> Sequence[OperandConstraint]
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return tuple(to_class if (reg is from_class) else reg for reg in regs)
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class TailRecipe:
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"""
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Generate encoding recipes on demand.
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Intel encodings are somewhat orthogonal with the opcode representation on
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one side and the ModR/M, SIB and immediate fields on the other side.
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A `TailRecipe` represents the part of an encoding that follow the opcode.
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It is used to generate full encoding recipes on demand when combined with
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an opcode.
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The arguments are the same as for an `EncRecipe`, except for `size` which
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does not include the size of the opcode.
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The `emit` parameter contains Rust code to actually emit an encoding, like
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`EncRecipe` does it. Additionally, the text `PUT_OP` is substituted with
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the proper `put_*` function from the `intel/binemit.rs` module.
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"""
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def __init__(
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self,
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name, # type: str
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format, # type: InstructionFormat
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size, # type: int
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ins, # type: ConstraintSeq
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outs, # type: ConstraintSeq
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branch_range=None, # type: BranchRange
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instp=None, # type: PredNode
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isap=None, # type: PredNode
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emit=None # type: str
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):
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# type: (...) -> None
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self.name = name
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self.format = format
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self.size = size
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self.ins = ins
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self.outs = outs
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self.branch_range = branch_range
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self.instp = instp
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self.isap = isap
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self.emit = emit
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# Cached recipes, keyed by name prefix.
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self.recipes = dict() # type: Dict[str, EncRecipe]
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def __call__(self, *ops, **kwargs):
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# type: (*int, **int) -> Tuple[EncRecipe, int]
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"""
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Create an encoding recipe and encoding bits for the opcode bytes in
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`ops`.
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"""
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rrr = kwargs.get('rrr', 0)
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w = kwargs.get('w', 0)
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name, bits = decode_ops(ops, rrr, w)
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if name not in self.recipes:
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recipe = EncRecipe(
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name + self.name,
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self.format,
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len(ops) + self.size,
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ins=self.ins,
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outs=self.outs,
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branch_range=self.branch_range,
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instp=self.instp,
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isap=self.isap,
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emit=replace_put_op(self.emit, name))
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recipe.ins = map_regs(recipe.ins, GPR, GPR8)
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recipe.ins = map_regs(recipe.ins, FPR, FPR8)
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recipe.outs = map_regs(recipe.outs, GPR, GPR8)
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recipe.outs = map_regs(recipe.outs, FPR, FPR8)
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self.recipes[name] = recipe
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return (self.recipes[name], bits)
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def rex(self, *ops, **kwargs):
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# type: (*int, **int) -> Tuple[EncRecipe, int]
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"""
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Create a REX encoding recipe and encoding bits for the opcode bytes in
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`ops`.
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The recipe will always generate a REX prefix, whether it is required or
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not. For instructions that don't require a REX prefix, two encodings
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should be added: One with REX and one without.
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"""
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rrr = kwargs.get('rrr', 0)
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w = kwargs.get('w', 0)
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name, bits = decode_ops(ops, rrr, w)
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name = 'Rex' + name
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if name not in self.recipes:
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self.recipes[name] = EncRecipe(
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name + self.name,
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self.format,
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1 + len(ops) + self.size,
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ins=self.ins,
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outs=self.outs,
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branch_range=self.branch_range,
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instp=self.instp,
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isap=self.isap,
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emit=replace_put_op(self.emit, name))
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return (self.recipes[name], bits)
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# A null unary instruction that takes a GPR register. Can be used for identity
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# copies and no-op conversions.
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null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
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# XX opcode, no ModR/M.
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trap = TailRecipe(
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'trap', Trap, size=0, ins=(), outs=(),
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emit='PUT_OP(bits, BASE_REX, sink);')
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# XX /r
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rr = TailRecipe(
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'rr', Binary, size=1, ins=(GPR, GPR), outs=0,
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emit='''
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PUT_OP(bits, rex2(in_reg0, in_reg1), sink);
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modrm_rr(in_reg0, in_reg1, sink);
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''')
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# XX /r with operands swapped. (RM form).
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rrx = TailRecipe(
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'rrx', Binary, size=1, ins=(GPR, GPR), outs=0,
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emit='''
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rr(in_reg1, in_reg0, sink);
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''')
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# XX /r with FPR ins and outs. RM form.
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frm = TailRecipe(
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'frr', Binary, size=1, ins=(FPR, FPR), outs=0,
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emit='''
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rr(in_reg1, in_reg0, sink);
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''')
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# XX /r, but for a unary operator with separate input/output register, like
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# copies. MR form.
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umr = TailRecipe(
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'umr', Unary, size=1, ins=GPR, outs=GPR,
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emit='''
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PUT_OP(bits, rex2(out_reg0, in_reg0), sink);
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modrm_rr(out_reg0, in_reg0, sink);
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''')
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# Same as umr, but with FPR -> GPR registers.
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rfumr = TailRecipe(
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'rfumr', Unary, size=1, ins=FPR, outs=GPR,
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emit='''
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PUT_OP(bits, rex2(out_reg0, in_reg0), sink);
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modrm_rr(out_reg0, in_reg0, sink);
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''')
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# XX /r, but for a unary operator with separate input/output register.
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# RM form.
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urm = TailRecipe(
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'urm', Unary, size=1, ins=GPR, outs=GPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r. Same as urm, but input limited to ABCD.
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urm_abcd = TailRecipe(
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'urm_abcd', Unary, size=1, ins=ABCD, outs=GPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r, RM form, FPR -> FPR.
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furm = TailRecipe(
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'furm', Unary, size=1, ins=FPR, outs=FPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r, RM form, GPR -> FPR.
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frurm = TailRecipe(
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'frurm', Unary, size=1, ins=GPR, outs=FPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r, RM form, FPR -> GPR.
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rfurm = TailRecipe(
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'rfurm', Unary, size=1, ins=FPR, outs=GPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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''')
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# XX /r, RMI form for one of the roundXX SSE 4.1 instructions.
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furmi_rnd = TailRecipe(
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'furmi_rnd', Unary, size=2, ins=FPR, outs=FPR,
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emit='''
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PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
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modrm_rr(in_reg0, out_reg0, sink);
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sink.put1(match opcode {
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Opcode::Nearest => 0b00,
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Opcode::Floor => 0b01,
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Opcode::Ceil => 0b10,
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Opcode::Trunc => 0b11,
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x => panic!("{} unexpected for furmi_rnd", opcode),
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});
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''')
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# XX /r, for regmove instructions.
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rmov = TailRecipe(
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'ur', RegMove, size=1, ins=GPR, outs=(),
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emit='''
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PUT_OP(bits, rex2(dst, src), sink);
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modrm_rr(dst, src, sink);
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''')
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# XX /n with one arg in %rcx, for shifts.
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rc = TailRecipe(
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'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,
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emit='''
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PUT_OP(bits, rex1(in_reg0), sink);
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modrm_r_bits(in_reg0, bits, sink);
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''')
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# XX /n for division: inputs in %rax, %rdx, r. Outputs in %rax, %rdx.
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div = TailRecipe(
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'div', Ternary, size=1,
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ins=(GPR.rax, GPR.rdx, GPR), outs=(GPR.rax, GPR.rdx),
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emit='''
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PUT_OP(bits, rex1(in_reg2), sink);
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modrm_r_bits(in_reg2, bits, sink);
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''')
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# XX /n ib with 8-bit immediate sign-extended.
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rib = TailRecipe(
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'rib', BinaryImm, size=2, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 8),
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emit='''
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PUT_OP(bits, rex1(in_reg0), sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put1(imm as u8);
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''')
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# XX /n id with 32-bit immediate sign-extended.
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rid = TailRecipe(
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'rid', BinaryImm, size=5, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 32),
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emit='''
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PUT_OP(bits, rex1(in_reg0), sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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''')
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# XX /n id with 32-bit immediate sign-extended. UnaryImm version.
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uid = TailRecipe(
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'uid', UnaryImm, size=5, ins=(), outs=GPR,
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instp=IsSignedInt(UnaryImm.imm, 32),
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emit='''
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PUT_OP(bits, rex1(out_reg0), sink);
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modrm_r_bits(out_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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''')
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# XX+rd id unary with 32-bit immediate. Note no recipe predicate.
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puid = TailRecipe(
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'uid', UnaryImm, size=4, ins=(), outs=GPR,
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emit='''
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// The destination register is encoded in the low bits of the opcode.
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// No ModR/M.
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PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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''')
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# XX+rd iq unary with 64-bit immediate.
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puiq = TailRecipe(
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'uiq', UnaryImm, size=8, ins=(), outs=GPR,
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emit='''
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PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
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let imm: i64 = imm.into();
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sink.put8(imm as u64);
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''')
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# XX+rd id with Abs4 function relocation.
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fnaddr4 = TailRecipe(
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'fnaddr4', FuncAddr, size=4, ins=(), outs=GPR,
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emit='''
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PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
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sink.reloc_func(RelocKind::Abs4.into(), func_ref);
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// Write the immediate as `!0` for the benefit of BaldrMonkey.
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sink.put4(!0);
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''')
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# XX+rd iq with Abs8 function relocation.
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fnaddr8 = TailRecipe(
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'fnaddr8', FuncAddr, size=8, ins=(), outs=GPR,
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emit='''
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PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
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sink.reloc_func(RelocKind::Abs8.into(), func_ref);
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// Write the immediate as `!0` for the benefit of BaldrMonkey.
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sink.put8(!0);
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''')
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#
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# Store recipes.
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#
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# XX /r register-indirect store with no offset.
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st = TailRecipe(
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'st', Store, size=1, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0),
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emit='''
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store with no offset.
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# Only ABCD allowed for stored value. This is for byte stores.
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st_abcd = TailRecipe(
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'st_abcd', Store, size=1, ins=(ABCD, GPR), outs=(),
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instp=IsEqual(Store.offset, 0),
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emit='''
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store of FPR with no offset.
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fst = TailRecipe(
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'fst', Store, size=1, ins=(FPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0),
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emit='''
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store with 8-bit offset.
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stDisp8 = TailRecipe(
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'stDisp8', Store, size=2, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8),
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|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp8(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put1(offset as u8);
|
|
''')
|
|
stDisp8_abcd = TailRecipe(
|
|
'stDisp8_abcd', Store, size=2, ins=(ABCD, GPR), outs=(),
|
|
instp=IsSignedInt(Store.offset, 8),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp8(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put1(offset as u8);
|
|
''')
|
|
fstDisp8 = TailRecipe(
|
|
'fstDisp8', Store, size=2, ins=(FPR, GPR), outs=(),
|
|
instp=IsSignedInt(Store.offset, 8),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp8(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put1(offset as u8);
|
|
''')
|
|
|
|
# XX /r register-indirect store with 32-bit offset.
|
|
stDisp32 = TailRecipe(
|
|
'stDisp32', Store, size=5, ins=(GPR, GPR), outs=(),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp32(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put4(offset as u32);
|
|
''')
|
|
stDisp32_abcd = TailRecipe(
|
|
'stDisp32_abcd', Store, size=5, ins=(ABCD, GPR), outs=(),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp32(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put4(offset as u32);
|
|
''')
|
|
fstDisp32 = TailRecipe(
|
|
'fstDisp32', Store, size=5, ins=(FPR, GPR), outs=(),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_disp32(in_reg1, in_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put4(offset as u32);
|
|
''')
|
|
|
|
# Unary spill with SIB and 32-bit displacement.
|
|
spSib32 = TailRecipe(
|
|
'spSib32', Unary, size=6, ins=GPR, outs=StackGPR32,
|
|
emit='''
|
|
let base = stk_base(out_stk0.base);
|
|
PUT_OP(bits, rex2(base, in_reg0), sink);
|
|
modrm_sib_disp32(in_reg0, sink);
|
|
sib_noindex(base, sink);
|
|
sink.put4(out_stk0.offset as u32);
|
|
''')
|
|
fspSib32 = TailRecipe(
|
|
'fspSib32', Unary, size=6, ins=FPR, outs=StackFPR32,
|
|
emit='''
|
|
let base = stk_base(out_stk0.base);
|
|
PUT_OP(bits, rex2(base, in_reg0), sink);
|
|
modrm_sib_disp32(in_reg0, sink);
|
|
sib_noindex(base, sink);
|
|
sink.put4(out_stk0.offset as u32);
|
|
''')
|
|
|
|
#
|
|
# Load recipes
|
|
#
|
|
|
|
# XX /r load with no offset.
|
|
ld = TailRecipe(
|
|
'ld', Load, size=1, ins=(GPR), outs=(GPR),
|
|
instp=IsEqual(Load.offset, 0),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_rm(in_reg0, out_reg0, sink);
|
|
''')
|
|
|
|
# XX /r float load with no offset.
|
|
fld = TailRecipe(
|
|
'fld', Load, size=1, ins=(GPR), outs=(FPR),
|
|
instp=IsEqual(Load.offset, 0),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_rm(in_reg0, out_reg0, sink);
|
|
''')
|
|
|
|
# XX /r load with 8-bit offset.
|
|
ldDisp8 = TailRecipe(
|
|
'ldDisp8', Load, size=2, ins=(GPR), outs=(GPR),
|
|
instp=IsSignedInt(Load.offset, 8),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_disp8(in_reg0, out_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put1(offset as u8);
|
|
''')
|
|
|
|
# XX /r float load with 8-bit offset.
|
|
fldDisp8 = TailRecipe(
|
|
'fldDisp8', Load, size=2, ins=(GPR), outs=(FPR),
|
|
instp=IsSignedInt(Load.offset, 8),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_disp8(in_reg0, out_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put1(offset as u8);
|
|
''')
|
|
|
|
# XX /r load with 32-bit offset.
|
|
ldDisp32 = TailRecipe(
|
|
'ldDisp32', Load, size=5, ins=(GPR), outs=(GPR),
|
|
instp=IsSignedInt(Load.offset, 32),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_disp32(in_reg0, out_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put4(offset as u32);
|
|
''')
|
|
|
|
# XX /r float load with 32-bit offset.
|
|
fldDisp32 = TailRecipe(
|
|
'fldDisp32', Load, size=5, ins=(GPR), outs=(FPR),
|
|
instp=IsSignedInt(Load.offset, 32),
|
|
emit='''
|
|
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
|
|
modrm_disp32(in_reg0, out_reg0, sink);
|
|
let offset: i32 = offset.into();
|
|
sink.put4(offset as u32);
|
|
''')
|
|
|
|
# Unary fill with SIB and 32-bit displacement.
|
|
fiSib32 = TailRecipe(
|
|
'fiSib32', Unary, size=6, ins=StackGPR32, outs=GPR,
|
|
emit='''
|
|
let base = stk_base(in_stk0.base);
|
|
PUT_OP(bits, rex2(base, out_reg0), sink);
|
|
modrm_sib_disp32(out_reg0, sink);
|
|
sib_noindex(base, sink);
|
|
sink.put4(in_stk0.offset as u32);
|
|
''')
|
|
ffiSib32 = TailRecipe(
|
|
'ffiSib32', Unary, size=6, ins=StackFPR32, outs=FPR,
|
|
emit='''
|
|
let base = stk_base(in_stk0.base);
|
|
PUT_OP(bits, rex2(base, out_reg0), sink);
|
|
modrm_sib_disp32(out_reg0, sink);
|
|
sib_noindex(base, sink);
|
|
sink.put4(in_stk0.offset as u32);
|
|
''')
|
|
|
|
#
|
|
# Call/return
|
|
#
|
|
call_id = TailRecipe(
|
|
'call_id', Call, size=4, ins=(), outs=(),
|
|
emit='''
|
|
PUT_OP(bits, BASE_REX, sink);
|
|
sink.reloc_func(RelocKind::PCRel4.into(), func_ref);
|
|
sink.put4(0);
|
|
''')
|
|
|
|
call_r = TailRecipe(
|
|
'call_r', IndirectCall, size=1, ins=GPR, outs=(),
|
|
emit='''
|
|
PUT_OP(bits, rex1(in_reg0), sink);
|
|
modrm_r_bits(in_reg0, bits, sink);
|
|
''')
|
|
|
|
ret = TailRecipe(
|
|
'ret', MultiAry, size=0, ins=(), outs=(),
|
|
emit='''
|
|
PUT_OP(bits, BASE_REX, sink);
|
|
''')
|
|
|
|
#
|
|
# Branches
|
|
#
|
|
jmpb = TailRecipe(
|
|
'jmpb', Jump, size=1, ins=(), outs=(),
|
|
branch_range=(2, 8),
|
|
emit='''
|
|
PUT_OP(bits, BASE_REX, sink);
|
|
disp1(destination, func, sink);
|
|
''')
|
|
|
|
jmpd = TailRecipe(
|
|
'jmpd', Jump, size=4, ins=(), outs=(),
|
|
branch_range=(5, 32),
|
|
emit='''
|
|
PUT_OP(bits, BASE_REX, sink);
|
|
disp4(destination, func, sink);
|
|
''')
|
|
|
|
# Test-and-branch.
|
|
#
|
|
# This recipe represents the macro fusion of a test and a conditional branch.
|
|
# This serves two purposes:
|
|
#
|
|
# 1. Guarantee that the test and branch get scheduled next to each other so
|
|
# macro fusion is guaranteed to be possible.
|
|
# 2. Hide the status flags from Cretonne which doesn't currently model flags.
|
|
#
|
|
# The encoding bits affect both the test and the branch instruction:
|
|
#
|
|
# Bits 0-7 are the Jcc opcode.
|
|
# Bits 8-15 control the test instruction which always has opcode byte 0x85.
|
|
tjccb = TailRecipe(
|
|
'tjcc', Branch, size=1 + 2, ins=GPR, outs=(),
|
|
branch_range=(2, 8),
|
|
emit='''
|
|
// test r, r.
|
|
PUT_OP((bits & 0xff00) | 0x85, rex2(in_reg0, in_reg0), sink);
|
|
modrm_rr(in_reg0, in_reg0, sink);
|
|
// Jcc instruction.
|
|
sink.put1(bits as u8);
|
|
disp1(destination, func, sink);
|
|
''')
|
|
|
|
# 8-bit test-and-branch.
|
|
#
|
|
# Same as tjccb, but only looks at the low 8 bits of the register, for b1
|
|
# types.
|
|
t8jccb_abcd = TailRecipe(
|
|
't8jccb_abcd', Branch, size=1 + 2, ins=ABCD, outs=(),
|
|
branch_range=(2, 8),
|
|
emit='''
|
|
// test8 r, r.
|
|
PUT_OP(0x84, rex2(in_reg0, in_reg0), sink);
|
|
modrm_rr(in_reg0, in_reg0, sink);
|
|
// Jcc instruction.
|
|
sink.put1(bits as u8);
|
|
disp1(destination, func, sink);
|
|
''')
|
|
|
|
# Comparison that produces a `b1` result in a GPR.
|
|
#
|
|
# This is a macro of a `cmp` instruction followed by a `setCC` instruction.
|
|
# This is not a great solution because:
|
|
#
|
|
# - The cmp+setcc combination is not recognized by CPU's macro fusion.
|
|
# - The 64-bit encoding has issues with REX prefixes. The `cmp` and `setCC`
|
|
# instructions may need a REX independently.
|
|
# - Modeling CPU flags in the type system would be better.
|
|
#
|
|
# Since the `setCC` instructions only write an 8-bit register, we use that as
|
|
# our `b1` representation: A `b1` value is represented as a GPR where the low 8
|
|
# bits are known to be 0 or 1. The high bits are undefined.
|
|
#
|
|
# This bandaid macro doesn't support a REX prefix for the final `setCC`
|
|
# instruction, so it is limited to the `ABCD` register class for booleans.
|
|
icscc = TailRecipe(
|
|
'icscc', IntCompare, size=1 + 3, ins=(GPR, GPR), outs=ABCD,
|
|
emit='''
|
|
// Comparison instruction.
|
|
PUT_OP(bits, rex2(in_reg0, in_reg1), sink);
|
|
modrm_rr(in_reg0, in_reg1, sink);
|
|
// `setCC` instruction, no REX.
|
|
use ir::condcodes::IntCC::*;
|
|
let setcc = match cond {
|
|
Equal => 0x94,
|
|
NotEqual => 0x95,
|
|
SignedLessThan => 0x9c,
|
|
SignedGreaterThanOrEqual => 0x9d,
|
|
SignedGreaterThan => 0x9f,
|
|
SignedLessThanOrEqual => 0x9e,
|
|
UnsignedLessThan => 0x92,
|
|
UnsignedGreaterThanOrEqual => 0x93,
|
|
UnsignedGreaterThan => 0x97,
|
|
UnsignedLessThanOrEqual => 0x96,
|
|
};
|
|
sink.put1(0x0f);
|
|
sink.put1(setcc);
|
|
modrm_rr(out_reg0, 0, sink);
|
|
''')
|
|
|
|
|
|
# Make a FloatCompare instruction predicate with the supported condition codes.
|
|
|
|
# Same thing for floating point.
|
|
#
|
|
# The ucomiss/ucomisd instructions set the EFLAGS bits CF/PF/CF like this:
|
|
#
|
|
# ZPC OSA
|
|
# UN 111 000
|
|
# GT 000 000
|
|
# LT 001 000
|
|
# EQ 100 000
|
|
#
|
|
# Not all floating point condition codes are supported.
|
|
fcscc = TailRecipe(
|
|
'fcscc', FloatCompare, size=1 + 3, ins=(FPR, FPR), outs=ABCD,
|
|
instp=Or(*(IsEqual(FloatCompare.cond, cc)
|
|
for cc in supported_floatccs)),
|
|
emit='''
|
|
// Comparison instruction.
|
|
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
|
|
modrm_rr(in_reg1, in_reg0, sink);
|
|
// `setCC` instruction, no REX.
|
|
use ir::condcodes::FloatCC::*;
|
|
let setcc = match cond {
|
|
Ordered => 0x9b, // EQ|LT|GT => setnp (P=0)
|
|
Unordered => 0x9a, // UN => setp (P=1)
|
|
OrderedNotEqual => 0x95, // LT|GT => setne (Z=0),
|
|
UnorderedOrEqual => 0x94, // UN|EQ => sete (Z=1)
|
|
GreaterThan => 0x97, // GT => seta (C=0&Z=0)
|
|
GreaterThanOrEqual => 0x93, // GT|EQ => setae (C=0)
|
|
UnorderedOrLessThan => 0x92, // UN|LT => setb (C=1)
|
|
UnorderedOrLessThanOrEqual => 0x96, // UN|LT|EQ => setbe (Z=1|C=1)
|
|
Equal | // EQ
|
|
NotEqual | // UN|LT|GT
|
|
LessThan | // LT
|
|
LessThanOrEqual | // LT|EQ
|
|
UnorderedOrGreaterThan | // UN|GT
|
|
UnorderedOrGreaterThanOrEqual // UN|GT|EQ
|
|
=> panic!("{} not supported by fcscc", cond),
|
|
};
|
|
sink.put1(0x0f);
|
|
sink.put1(setcc);
|
|
modrm_rr(out_reg0, 0, sink);
|
|
''')
|