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Merge pull request #3655 from bjorn3/machinst_cleanups2

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Remove MachBackend
This commit is contained in:
Chris Fallin
2022-01-06 13:32:36 -08:00
committed by GitHub
parent 72e2b7fe80 376c93bda0
commit a98f9982fd
14 changed files with 116 additions and 220 deletions
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4
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -2017,10 +2017,6 @@ impl MachInst for Inst {
}
}
fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
create_reg_universe(flags)
}
fn worst_case_size() -> CodeOffset {
// The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
// an 8-instruction sequence (saturating int-to-float conversions) with three embedded

26
cranelift/codegen/src/isa/aarch64/mod.rs
View File

@@ -3,14 +3,14 @@
use crate::ir::condcodes::IntCC;
use crate::ir::Function;
use crate::isa::aarch64::settings as aarch64_settings;
use crate::isa::Builder as IsaBuilder;
use crate::isa::{Builder as IsaBuilder, TargetIsa};
use crate::machinst::{
compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter,
TextSectionBuilder, VCode,
compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
};
use crate::result::CodegenResult;
use crate::settings as shared_settings;
use alloc::{boxed::Box, vec::Vec};
use core::fmt;
use regalloc::{PrettyPrint, RealRegUniverse};
use target_lexicon::{Aarch64Architecture, Architecture, Triple};
@@ -58,11 +58,11 @@ impl AArch64Backend {
) -> CodegenResult<VCode<inst::Inst>> {
let emit_info = EmitInfo::new(flags.clone());
let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?);
compile::compile::<AArch64Backend>(func, self, abi, emit_info)
compile::compile::<AArch64Backend>(func, self, abi, &self.reg_universe, emit_info)
}
}
impl MachBackend for AArch64Backend {
impl TargetIsa for AArch64Backend {
fn compile_function(
&self,
func: &Function,
@@ -110,10 +110,6 @@ impl MachBackend for AArch64Backend {
self.isa_flags.iter().collect()
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
fn unsigned_add_overflow_condition(&self) -> IntCC {
// Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on
// overflow of an add.
@@ -157,6 +153,16 @@ impl MachBackend for AArch64Backend {
}
}
impl fmt::Display for AArch64Backend {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("MachBackend")
.field("name", &self.name())
.field("triple", &self.triple())
.field("flags", &format!("{}", self.flags()))
.finish()
}
}
/// Create a new `isa::Builder`.
pub fn isa_builder(triple: Triple) -> IsaBuilder {
assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64));
@@ -166,7 +172,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder {
constructor: |triple, shared_flags, builder| {
let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder);
let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags);
Box::new(TargetIsaAdapter::new(backend))
Box::new(backend)
},
}
}

4
cranelift/codegen/src/isa/arm32/inst/mod.rs
View File

@@ -859,10 +859,6 @@ impl MachInst for Inst {
}
}
fn reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
create_reg_universe()
}
fn worst_case_size() -> CodeOffset {
// It inst with four 32-bit instructions
2 + 4 * 4

31
cranelift/codegen/src/isa/arm32/mod.rs
View File

@@ -2,15 +2,15 @@
use crate::ir::condcodes::IntCC;
use crate::ir::Function;
use crate::isa::Builder as IsaBuilder;
use crate::isa::{Builder as IsaBuilder, TargetIsa};
use crate::machinst::{
compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter,
TextSectionBuilder, VCode,
compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
};
use crate::result::CodegenResult;
use crate::settings;
use alloc::{boxed::Box, vec::Vec};
use core::fmt;
use regalloc::{PrettyPrint, RealRegUniverse};
use target_lexicon::{Architecture, ArmArchitecture, Triple};
@@ -49,11 +49,11 @@ impl Arm32Backend {
// block layout and finalizes branches. The result is ready for binary emission.
let emit_info = EmitInfo::new(flags.clone());
let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
compile::compile::<Arm32Backend>(func, self, abi, emit_info)
compile::compile::<Arm32Backend>(func, self, abi, &self.reg_universe, emit_info)
}
}
impl MachBackend for Arm32Backend {
impl TargetIsa for Arm32Backend {
fn compile_function(
&self,
func: &Function,
@@ -100,8 +100,13 @@ impl MachBackend for Arm32Backend {
Vec::new()
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
#[cfg(feature = "unwind")]
fn emit_unwind_info(
&self,
_result: &MachCompileResult,
_kind: crate::machinst::UnwindInfoKind,
) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
Ok(None) // FIXME implement this
}
fn unsigned_add_overflow_condition(&self) -> IntCC {
@@ -114,6 +119,16 @@ impl MachBackend for Arm32Backend {
}
}
impl fmt::Display for Arm32Backend {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("MachBackend")
.field("name", &self.name())
.field("triple", &self.triple())
.field("flags", &format!("{}", self.flags()))
.finish()
}
}
/// Create a new `isa::Builder`.
pub fn isa_builder(triple: Triple) -> IsaBuilder {
assert!(match triple.architecture {
@@ -127,7 +142,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder {
setup: settings::builder(),
constructor: |triple, shared_flags, _| {
let backend = Arm32Backend::new_with_flags(triple, shared_flags);
Box::new(TargetIsaAdapter::new(backend))
Box::new(backend)
},
}
}

34
cranelift/codegen/src/isa/mod.rs
View File

@@ -46,12 +46,13 @@
pub use crate::isa::call_conv::CallConv;
use crate::flowgraph;
use crate::ir;
use crate::ir::{self, Function};
#[cfg(feature = "unwind")]
use crate::isa::unwind::systemv::RegisterMappingError;
use crate::machinst::{MachBackend, UnwindInfoKind};
use crate::machinst::{MachCompileResult, TextSectionBuilder, UnwindInfoKind};
use crate::settings;
use crate::settings::SetResult;
use crate::CodegenResult;
use alloc::{boxed::Box, vec::Vec};
use core::fmt;
use core::fmt::{Debug, Formatter};
@@ -227,6 +228,13 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
/// Get the ISA-dependent flag values that were used to make this trait object.
fn isa_flags(&self) -> Vec<settings::Value>;
/// Compile the given function.
fn compile_function(
&self,
func: &Function,
want_disasm: bool,
) -> CodegenResult<MachCompileResult>;
#[cfg(feature = "unwind")]
/// Map a regalloc::Reg to its corresponding DWARF register.
fn map_regalloc_reg_to_dwarf(&self, _: ::regalloc::Reg) -> Result<u16, RegisterMappingError> {
@@ -236,6 +244,16 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
/// IntCC condition for Unsigned Addition Overflow (Carry).
fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC;
/// Creates unwind information for the function.
///
/// Returns `None` if there is no unwind information for the function.
#[cfg(feature = "unwind")]
fn emit_unwind_info(
&self,
result: &MachCompileResult,
kind: UnwindInfoKind,
) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>>;
/// Creates a new System V Common Information Entry for the ISA.
///
/// Returns `None` if the ISA does not support System V unwind information.
@@ -245,8 +263,16 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
None
}
/// Get the new-style MachBackend.
fn get_mach_backend(&self) -> &dyn MachBackend;
/// Returns an object that can be used to build the text section of an
/// executable.
///
/// This object will internally attempt to handle as many relocations as
/// possible using relative calls/jumps/etc between functions.
///
/// The `num_labeled_funcs` argument here is the number of functions which
/// will be "labeled" or might have calls between them, typically the number
/// of defined functions in the object file.
fn text_section_builder(&self, num_labeled_funcs: u32) -> Box<dyn TextSectionBuilder>;
}
/// Methods implemented for free for target ISA!

4
cranelift/codegen/src/isa/s390x/inst/mod.rs
View File

@@ -2507,10 +2507,6 @@ impl MachInst for Inst {
}
}
fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
create_reg_universe(flags)
}
fn worst_case_size() -> CodeOffset {
// The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
// an 8-instruction sequence (saturating int-to-float conversions) with three embedded

28
cranelift/codegen/src/isa/s390x/mod.rs
View File

@@ -5,15 +5,15 @@ use crate::ir::Function;
use crate::isa::s390x::settings as s390x_settings;
#[cfg(feature = "unwind")]
use crate::isa::unwind::systemv::RegisterMappingError;
use crate::isa::Builder as IsaBuilder;
use crate::isa::{Builder as IsaBuilder, TargetIsa};
use crate::machinst::{
compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter,
TextSectionBuilder, VCode,
compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
};
use crate::result::CodegenResult;
use crate::settings as shared_settings;
use alloc::{boxed::Box, vec::Vec};
use core::fmt;
use regalloc::{PrettyPrint, RealRegUniverse, Reg};
use target_lexicon::{Architecture, Triple};
@@ -61,11 +61,11 @@ impl S390xBackend {
) -> CodegenResult<VCode<inst::Inst>> {
let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
let abi = Box::new(abi::S390xABICallee::new(func, flags)?);
compile::compile::<S390xBackend>(func, self, abi, emit_info)
compile::compile::<S390xBackend>(func, self, abi, &self.reg_universe, emit_info)
}
}
impl MachBackend for S390xBackend {
impl TargetIsa for S390xBackend {
fn compile_function(
&self,
func: &Function,
@@ -113,10 +113,6 @@ impl MachBackend for S390xBackend {
self.isa_flags.iter().collect()
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
fn unsigned_add_overflow_condition(&self) -> IntCC {
// The ADD LOGICAL family of instructions set the condition code
// differently from normal comparisons, in a way that cannot be
@@ -155,7 +151,7 @@ impl MachBackend for S390xBackend {
}
#[cfg(feature = "unwind")]
fn map_reg_to_dwarf(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
}
@@ -164,6 +160,16 @@ impl MachBackend for S390xBackend {
}
}
impl fmt::Display for S390xBackend {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("MachBackend")
.field("name", &self.name())
.field("triple", &self.triple())
.field("flags", &format!("{}", self.flags()))
.finish()
}
}
/// Create a new `isa::Builder`.
pub fn isa_builder(triple: Triple) -> IsaBuilder {
assert!(triple.architecture == Architecture::S390x);
@@ -173,7 +179,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder {
constructor: |triple, shared_flags, builder| {
let isa_flags = s390x_settings::Flags::new(&shared_flags, builder);
let backend = S390xBackend::new_with_flags(triple, shared_flags, isa_flags);
Box::new(TargetIsaAdapter::new(backend))
Box::new(backend)
},
}
}

8
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -7,7 +7,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec;
use crate::isa::x64::settings as x64_settings;
use crate::isa::CallConv;
use crate::machinst::*;
use crate::{settings, settings::Flags, CodegenError, CodegenResult};
use crate::{settings, CodegenError, CodegenResult};
use alloc::boxed::Box;
use alloc::vec::Vec;
use regalloc::{
@@ -26,7 +26,7 @@ pub mod regs;
pub mod unwind;
use args::*;
use regs::{create_reg_universe_systemv, show_ireg_sized};
use regs::show_ireg_sized;
//=============================================================================
// Instructions (top level): definition
@@ -3226,10 +3226,6 @@ impl MachInst for Inst {
ret
}
fn reg_universe(flags: &Flags) -> RealRegUniverse {
create_reg_universe_systemv(flags)
}
fn worst_case_size() -> CodeOffset {
15
}

26
cranelift/codegen/src/isa/x64/mod.rs
View File

@@ -9,12 +9,12 @@ use crate::isa::unwind::systemv;
use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
use crate::isa::Builder as IsaBuilder;
use crate::machinst::{
compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter,
TextSectionBuilder, VCode,
compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
};
use crate::result::CodegenResult;
use crate::settings::{self as shared_settings, Flags};
use alloc::{boxed::Box, vec::Vec};
use core::fmt;
use regalloc::{PrettyPrint, RealRegUniverse, Reg};
use target_lexicon::Triple;
@@ -50,11 +50,11 @@ impl X64Backend {
// block layout and finalizes branches. The result is ready for binary emission.
let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
let abi = Box::new(abi::X64ABICallee::new(&func, flags)?);
compile::compile::<Self>(&func, self, abi, emit_info)
compile::compile::<Self>(&func, self, abi, &self.reg_universe, emit_info)
}
}
impl MachBackend for X64Backend {
impl TargetIsa for X64Backend {
fn compile_function(
&self,
func: &Function,
@@ -102,10 +102,6 @@ impl MachBackend for X64Backend {
&self.triple
}
fn reg_universe(&self) -> &RealRegUniverse {
&self.reg_universe
}
fn unsigned_add_overflow_condition(&self) -> IntCC {
// Unsigned `<`; this corresponds to the carry flag set on x86, which
// indicates an add has overflowed.
@@ -146,7 +142,7 @@ impl MachBackend for X64Backend {
}
#[cfg(feature = "unwind")]
fn map_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
}
@@ -155,6 +151,16 @@ impl MachBackend for X64Backend {
}
}
impl fmt::Display for X64Backend {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("MachBackend")
.field("name", &self.name())
.field("triple", &self.triple())
.field("flags", &format!("{}", self.flags()))
.finish()
}
}
/// Create a new `isa::Builder`.
pub(crate) fn isa_builder(triple: Triple) -> IsaBuilder {
IsaBuilder {
@@ -171,5 +177,5 @@ fn isa_constructor(
) -> Box<dyn TargetIsa> {
let isa_flags = x64_settings::Flags::new(&shared_flags, builder);
let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags);
Box::new(TargetIsaAdapter::new(backend))
Box::new(backend)
}