diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs index d416ef8be2..67fc48d77c 100644 --- a/cranelift/codegen/src/context.rs +++ b/cranelift/codegen/src/context.rs @@ -167,8 +167,7 @@ impl Context { self.remove_constant_phis(isa)?; - let backend = isa.get_mach_backend(); - let result = backend.compile_function(&self.func, self.want_disasm)?; + let result = isa.compile_function(&self.func, self.want_disasm)?; let info = result.code_info(); self.mach_compile_result = Some(result); Ok(info) @@ -242,10 +241,9 @@ impl Context { &self, isa: &dyn TargetIsa, ) -> CodegenResult> { - let backend = isa.get_mach_backend(); let unwind_info_kind = isa.unwind_info_kind(); let result = self.mach_compile_result.as_ref().unwrap(); - backend.emit_unwind_info(result, unwind_info_kind) + isa.emit_unwind_info(result, unwind_info_kind) } /// Run the verifier on the function. diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 83d878b746..66a6e536d5 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -2017,10 +2017,6 @@ impl MachInst for Inst { } } - fn reg_universe(flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe(flags) - } - fn worst_case_size() -> CodeOffset { // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of // an 8-instruction sequence (saturating int-to-float conversions) with three embedded diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs index 06302d820d..ae19034dd9 100644 --- a/cranelift/codegen/src/isa/aarch64/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/mod.rs @@ -3,14 +3,14 @@ use crate::ir::condcodes::IntCC; use crate::ir::Function; use crate::isa::aarch64::settings as aarch64_settings; -use crate::isa::Builder as IsaBuilder; +use crate::isa::{Builder as IsaBuilder, TargetIsa}; use crate::machinst::{ - compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter, - TextSectionBuilder, VCode, + compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode, }; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::{boxed::Box, vec::Vec}; +use core::fmt; use regalloc::{PrettyPrint, RealRegUniverse}; use target_lexicon::{Aarch64Architecture, Architecture, Triple}; @@ -58,11 +58,11 @@ impl AArch64Backend { ) -> CodegenResult> { let emit_info = EmitInfo::new(flags.clone()); let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?); - compile::compile::(func, self, abi, emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } -impl MachBackend for AArch64Backend { +impl TargetIsa for AArch64Backend { fn compile_function( &self, func: &Function, @@ -110,10 +110,6 @@ impl MachBackend for AArch64Backend { self.isa_flags.iter().collect() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on // overflow of an add. @@ -157,6 +153,16 @@ impl MachBackend for AArch64Backend { } } +impl fmt::Display for AArch64Backend { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("MachBackend") + .field("name", &self.name()) + .field("triple", &self.triple()) + .field("flags", &format!("{}", self.flags())) + .finish() + } +} + /// Create a new `isa::Builder`. pub fn isa_builder(triple: Triple) -> IsaBuilder { assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64)); @@ -166,7 +172,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { constructor: |triple, shared_flags, builder| { let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder); let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags); - Box::new(TargetIsaAdapter::new(backend)) + Box::new(backend) }, } } diff --git a/cranelift/codegen/src/isa/arm32/inst/mod.rs b/cranelift/codegen/src/isa/arm32/inst/mod.rs index 8151eab818..7cba5d6c1c 100644 --- a/cranelift/codegen/src/isa/arm32/inst/mod.rs +++ b/cranelift/codegen/src/isa/arm32/inst/mod.rs @@ -859,10 +859,6 @@ impl MachInst for Inst { } } - fn reg_universe(_flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe() - } - fn worst_case_size() -> CodeOffset { // It inst with four 32-bit instructions 2 + 4 * 4 diff --git a/cranelift/codegen/src/isa/arm32/mod.rs b/cranelift/codegen/src/isa/arm32/mod.rs index f80f0d1d5c..f6a5ba8267 100644 --- a/cranelift/codegen/src/isa/arm32/mod.rs +++ b/cranelift/codegen/src/isa/arm32/mod.rs @@ -2,15 +2,15 @@ use crate::ir::condcodes::IntCC; use crate::ir::Function; -use crate::isa::Builder as IsaBuilder; +use crate::isa::{Builder as IsaBuilder, TargetIsa}; use crate::machinst::{ - compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter, - TextSectionBuilder, VCode, + compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode, }; use crate::result::CodegenResult; use crate::settings; use alloc::{boxed::Box, vec::Vec}; +use core::fmt; use regalloc::{PrettyPrint, RealRegUniverse}; use target_lexicon::{Architecture, ArmArchitecture, Triple}; @@ -49,11 +49,11 @@ impl Arm32Backend { // block layout and finalizes branches. The result is ready for binary emission. let emit_info = EmitInfo::new(flags.clone()); let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?); - compile::compile::(func, self, abi, emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } -impl MachBackend for Arm32Backend { +impl TargetIsa for Arm32Backend { fn compile_function( &self, func: &Function, @@ -100,8 +100,13 @@ impl MachBackend for Arm32Backend { Vec::new() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe + #[cfg(feature = "unwind")] + fn emit_unwind_info( + &self, + _result: &MachCompileResult, + _kind: crate::machinst::UnwindInfoKind, + ) -> CodegenResult> { + Ok(None) // FIXME implement this } fn unsigned_add_overflow_condition(&self) -> IntCC { @@ -114,6 +119,16 @@ impl MachBackend for Arm32Backend { } } +impl fmt::Display for Arm32Backend { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("MachBackend") + .field("name", &self.name()) + .field("triple", &self.triple()) + .field("flags", &format!("{}", self.flags())) + .finish() + } +} + /// Create a new `isa::Builder`. pub fn isa_builder(triple: Triple) -> IsaBuilder { assert!(match triple.architecture { @@ -127,7 +142,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { setup: settings::builder(), constructor: |triple, shared_flags, _| { let backend = Arm32Backend::new_with_flags(triple, shared_flags); - Box::new(TargetIsaAdapter::new(backend)) + Box::new(backend) }, } } diff --git a/cranelift/codegen/src/isa/mod.rs b/cranelift/codegen/src/isa/mod.rs index ce034ec01f..e92dc21627 100644 --- a/cranelift/codegen/src/isa/mod.rs +++ b/cranelift/codegen/src/isa/mod.rs @@ -46,12 +46,13 @@ pub use crate::isa::call_conv::CallConv; use crate::flowgraph; -use crate::ir; +use crate::ir::{self, Function}; #[cfg(feature = "unwind")] use crate::isa::unwind::systemv::RegisterMappingError; -use crate::machinst::{MachBackend, UnwindInfoKind}; +use crate::machinst::{MachCompileResult, TextSectionBuilder, UnwindInfoKind}; use crate::settings; use crate::settings::SetResult; +use crate::CodegenResult; use alloc::{boxed::Box, vec::Vec}; use core::fmt; use core::fmt::{Debug, Formatter}; @@ -227,6 +228,13 @@ pub trait TargetIsa: fmt::Display + Send + Sync { /// Get the ISA-dependent flag values that were used to make this trait object. fn isa_flags(&self) -> Vec; + /// Compile the given function. + fn compile_function( + &self, + func: &Function, + want_disasm: bool, + ) -> CodegenResult; + #[cfg(feature = "unwind")] /// Map a regalloc::Reg to its corresponding DWARF register. fn map_regalloc_reg_to_dwarf(&self, _: ::regalloc::Reg) -> Result { @@ -236,6 +244,16 @@ pub trait TargetIsa: fmt::Display + Send + Sync { /// IntCC condition for Unsigned Addition Overflow (Carry). fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC; + /// Creates unwind information for the function. + /// + /// Returns `None` if there is no unwind information for the function. + #[cfg(feature = "unwind")] + fn emit_unwind_info( + &self, + result: &MachCompileResult, + kind: UnwindInfoKind, + ) -> CodegenResult>; + /// Creates a new System V Common Information Entry for the ISA. /// /// Returns `None` if the ISA does not support System V unwind information. @@ -245,8 +263,16 @@ pub trait TargetIsa: fmt::Display + Send + Sync { None } - /// Get the new-style MachBackend. - fn get_mach_backend(&self) -> &dyn MachBackend; + /// Returns an object that can be used to build the text section of an + /// executable. + /// + /// This object will internally attempt to handle as many relocations as + /// possible using relative calls/jumps/etc between functions. + /// + /// The `num_labeled_funcs` argument here is the number of functions which + /// will be "labeled" or might have calls between them, typically the number + /// of defined functions in the object file. + fn text_section_builder(&self, num_labeled_funcs: u32) -> Box; } /// Methods implemented for free for target ISA! diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 74406cd8df..b48b4fb2a7 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -2507,10 +2507,6 @@ impl MachInst for Inst { } } - fn reg_universe(flags: &settings::Flags) -> RealRegUniverse { - create_reg_universe(flags) - } - fn worst_case_size() -> CodeOffset { // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of // an 8-instruction sequence (saturating int-to-float conversions) with three embedded diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs index 3c888a537a..dbf8679924 100644 --- a/cranelift/codegen/src/isa/s390x/mod.rs +++ b/cranelift/codegen/src/isa/s390x/mod.rs @@ -5,15 +5,15 @@ use crate::ir::Function; use crate::isa::s390x::settings as s390x_settings; #[cfg(feature = "unwind")] use crate::isa::unwind::systemv::RegisterMappingError; -use crate::isa::Builder as IsaBuilder; +use crate::isa::{Builder as IsaBuilder, TargetIsa}; use crate::machinst::{ - compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter, - TextSectionBuilder, VCode, + compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode, }; use crate::result::CodegenResult; use crate::settings as shared_settings; use alloc::{boxed::Box, vec::Vec}; +use core::fmt; use regalloc::{PrettyPrint, RealRegUniverse, Reg}; use target_lexicon::{Architecture, Triple}; @@ -61,11 +61,11 @@ impl S390xBackend { ) -> CodegenResult> { let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone()); let abi = Box::new(abi::S390xABICallee::new(func, flags)?); - compile::compile::(func, self, abi, emit_info) + compile::compile::(func, self, abi, &self.reg_universe, emit_info) } } -impl MachBackend for S390xBackend { +impl TargetIsa for S390xBackend { fn compile_function( &self, func: &Function, @@ -113,10 +113,6 @@ impl MachBackend for S390xBackend { self.isa_flags.iter().collect() } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // The ADD LOGICAL family of instructions set the condition code // differently from normal comparisons, in a way that cannot be @@ -155,7 +151,7 @@ impl MachBackend for S390xBackend { } #[cfg(feature = "unwind")] - fn map_reg_to_dwarf(&self, reg: Reg) -> Result { + fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result { inst::unwind::systemv::map_reg(reg).map(|reg| reg.0) } @@ -164,6 +160,16 @@ impl MachBackend for S390xBackend { } } +impl fmt::Display for S390xBackend { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("MachBackend") + .field("name", &self.name()) + .field("triple", &self.triple()) + .field("flags", &format!("{}", self.flags())) + .finish() + } +} + /// Create a new `isa::Builder`. pub fn isa_builder(triple: Triple) -> IsaBuilder { assert!(triple.architecture == Architecture::S390x); @@ -173,7 +179,7 @@ pub fn isa_builder(triple: Triple) -> IsaBuilder { constructor: |triple, shared_flags, builder| { let isa_flags = s390x_settings::Flags::new(&shared_flags, builder); let backend = S390xBackend::new_with_flags(triple, shared_flags, isa_flags); - Box::new(TargetIsaAdapter::new(backend)) + Box::new(backend) }, } } diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index f40d3c46e3..7dfb5d7304 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -7,7 +7,7 @@ use crate::isa::x64::abi::X64ABIMachineSpec; use crate::isa::x64::settings as x64_settings; use crate::isa::CallConv; use crate::machinst::*; -use crate::{settings, settings::Flags, CodegenError, CodegenResult}; +use crate::{settings, CodegenError, CodegenResult}; use alloc::boxed::Box; use alloc::vec::Vec; use regalloc::{ @@ -26,7 +26,7 @@ pub mod regs; pub mod unwind; use args::*; -use regs::{create_reg_universe_systemv, show_ireg_sized}; +use regs::show_ireg_sized; //============================================================================= // Instructions (top level): definition @@ -3226,10 +3226,6 @@ impl MachInst for Inst { ret } - fn reg_universe(flags: &Flags) -> RealRegUniverse { - create_reg_universe_systemv(flags) - } - fn worst_case_size() -> CodeOffset { 15 } diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs index bb0b1a5352..7e4c4f277b 100644 --- a/cranelift/codegen/src/isa/x64/mod.rs +++ b/cranelift/codegen/src/isa/x64/mod.rs @@ -9,12 +9,12 @@ use crate::isa::unwind::systemv; use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings}; use crate::isa::Builder as IsaBuilder; use crate::machinst::{ - compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter, - TextSectionBuilder, VCode, + compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode, }; use crate::result::CodegenResult; use crate::settings::{self as shared_settings, Flags}; use alloc::{boxed::Box, vec::Vec}; +use core::fmt; use regalloc::{PrettyPrint, RealRegUniverse, Reg}; use target_lexicon::Triple; @@ -50,11 +50,11 @@ impl X64Backend { // block layout and finalizes branches. The result is ready for binary emission. let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone()); let abi = Box::new(abi::X64ABICallee::new(&func, flags)?); - compile::compile::(&func, self, abi, emit_info) + compile::compile::(&func, self, abi, &self.reg_universe, emit_info) } } -impl MachBackend for X64Backend { +impl TargetIsa for X64Backend { fn compile_function( &self, func: &Function, @@ -102,10 +102,6 @@ impl MachBackend for X64Backend { &self.triple } - fn reg_universe(&self) -> &RealRegUniverse { - &self.reg_universe - } - fn unsigned_add_overflow_condition(&self) -> IntCC { // Unsigned `<`; this corresponds to the carry flag set on x86, which // indicates an add has overflowed. @@ -146,7 +142,7 @@ impl MachBackend for X64Backend { } #[cfg(feature = "unwind")] - fn map_reg_to_dwarf(&self, reg: Reg) -> Result { + fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result { inst::unwind::systemv::map_reg(reg).map(|reg| reg.0) } @@ -155,6 +151,16 @@ impl MachBackend for X64Backend { } } +impl fmt::Display for X64Backend { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("MachBackend") + .field("name", &self.name()) + .field("triple", &self.triple()) + .field("flags", &format!("{}", self.flags())) + .finish() + } +} + /// Create a new `isa::Builder`. pub(crate) fn isa_builder(triple: Triple) -> IsaBuilder { IsaBuilder { @@ -171,5 +177,5 @@ fn isa_constructor( ) -> Box { let isa_flags = x64_settings::Flags::new(&shared_flags, builder); let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags); - Box::new(TargetIsaAdapter::new(backend)) + Box::new(backend) } diff --git a/cranelift/codegen/src/machinst/adapter.rs b/cranelift/codegen/src/machinst/adapter.rs deleted file mode 100644 index c3f0bc9d97..0000000000 --- a/cranelift/codegen/src/machinst/adapter.rs +++ /dev/null @@ -1,72 +0,0 @@ -//! Adapter for a `MachBackend` to implement the `TargetIsa` trait. - -use crate::ir; -use crate::isa::TargetIsa; -use crate::machinst::*; -use crate::settings::{self, Flags}; - -#[cfg(feature = "unwind")] -use crate::isa::unwind::systemv::RegisterMappingError; - -use std::fmt; -use target_lexicon::Triple; - -/// A wrapper around a `MachBackend` that provides a `TargetIsa` impl. -pub struct TargetIsaAdapter { - backend: Box, -} - -impl TargetIsaAdapter { - /// Create a new `TargetIsa` wrapper around a `MachBackend`. - pub fn new(backend: B) -> TargetIsaAdapter { - TargetIsaAdapter { - backend: Box::new(backend), - } - } -} - -impl fmt::Display for TargetIsaAdapter { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - f.debug_struct("MachBackend") - .field("name", &self.backend.name()) - .field("triple", &self.backend.triple()) - .field("flags", &format!("{}", self.backend.flags())) - .finish() - } -} - -impl TargetIsa for TargetIsaAdapter { - fn name(&self) -> &'static str { - self.backend.name() - } - - fn triple(&self) -> &Triple { - self.backend.triple() - } - - fn flags(&self) -> &Flags { - self.backend.flags() - } - - fn isa_flags(&self) -> Vec { - self.backend.isa_flags() - } - - fn get_mach_backend(&self) -> &dyn MachBackend { - &*self.backend - } - - fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC { - self.backend.unsigned_add_overflow_condition() - } - - #[cfg(feature = "unwind")] - fn create_systemv_cie(&self) -> Option { - self.backend.create_systemv_cie() - } - - #[cfg(feature = "unwind")] - fn map_regalloc_reg_to_dwarf(&self, r: Reg) -> Result { - self.backend.map_reg_to_dwarf(r) - } -} diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs index 1f53a5b9e5..67593d940a 100644 --- a/cranelift/codegen/src/machinst/compile.rs +++ b/cranelift/codegen/src/machinst/compile.rs @@ -1,6 +1,7 @@ //! Compilation backend pipeline: optimized IR to VCode / binemit. use crate::ir::Function; +use crate::isa::TargetIsa; use crate::log::DeferredDisplay; use crate::machinst::*; use crate::settings; @@ -10,10 +11,11 @@ use regalloc::{allocate_registers_with_opts, Algorithm, Options, PrettyPrint}; /// Compile the given function down to VCode with allocated registers, ready /// for binary emission. -pub fn compile( +pub fn compile( f: &Function, b: &B, abi: Box>, + reg_universe: &RealRegUniverse, emit_info: ::Info, ) -> CodegenResult> where @@ -33,7 +35,7 @@ where // rendering. log::trace!( "vcode from lowering: \n{}", - DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe()))) + DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe))) ); // Perform register allocation. @@ -55,7 +57,7 @@ where use std::fs; use std::path::Path; if let Some(path) = std::env::var("SERIALIZE_REGALLOC").ok() { - let snapshot = regalloc::IRSnapshot::from_function(&vcode, b.reg_universe()); + let snapshot = regalloc::IRSnapshot::from_function(&vcode, reg_universe); let serialized = bincode::serialize(&snapshot).expect("couldn't serialize snapshot"); let file_path = Path::new(&path).join(Path::new(&format!("ir{}.bin", f.name))); @@ -78,7 +80,7 @@ where let _tt = timing::regalloc(); allocate_registers_with_opts( &mut vcode, - b.reg_universe(), + reg_universe, sri, Options { run_checker, @@ -88,7 +90,7 @@ where .map_err(|err| { log::error!( "Register allocation error for vcode\n{}\nError: {:?}", - vcode.show_rru(Some(b.reg_universe())), + vcode.show_rru(Some(reg_universe)), err ); err @@ -105,7 +107,7 @@ where log::trace!( "vcode after regalloc: final version:\n{}", - DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe()))) + DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe))) ); Ok(vcode) diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs index de491f2ace..e16dcce9a0 100644 --- a/cranelift/codegen/src/machinst/mod.rs +++ b/cranelift/codegen/src/machinst/mod.rs @@ -61,10 +61,9 @@ //! ``` use crate::binemit::{Addend, CodeInfo, CodeOffset, Reloc, StackMap}; -use crate::ir::condcodes::IntCC; -use crate::ir::{Function, SourceLoc, StackSlot, Type, ValueLabel}; +use crate::ir::{SourceLoc, StackSlot, Type, ValueLabel}; use crate::result::CodegenResult; -use crate::settings::{self, Flags}; +use crate::settings::Flags; use crate::value_label::ValueLabelsRanges; use alloc::boxed::Box; use alloc::vec::Vec; @@ -76,10 +75,6 @@ use regalloc::{ }; use smallvec::{smallvec, SmallVec}; use std::string::String; -use target_lexicon::Triple; - -#[cfg(feature = "unwind")] -use crate::isa::unwind::systemv::RegisterMappingError; #[macro_use] pub mod isle; @@ -98,8 +93,6 @@ pub mod abi_impl; pub use abi_impl::*; pub mod buffer; pub use buffer::*; -pub mod adapter; -pub use adapter::*; pub mod helpers; pub use helpers::*; pub mod inst_common; @@ -181,9 +174,6 @@ pub trait MachInst: Clone + Debug { /// the instruction must have a nonzero size if preferred_size is nonzero. fn gen_nop(preferred_size: usize) -> Self; - /// Get the register universe for this backend. - fn reg_universe(flags: &Flags) -> RealRegUniverse; - /// Align a basic block offset (from start of function). By default, no /// alignment occurs. fn align_basic_block(offset: CodeOffset) -> CodeOffset { @@ -366,70 +356,6 @@ impl MachCompileResult { } } -/// Top-level machine backend trait, which wraps all monomorphized code and -/// allows a virtual call from the machine-independent `Function::compile()`. -pub trait MachBackend { - /// Compile the given function. - fn compile_function( - &self, - func: &Function, - want_disasm: bool, - ) -> CodegenResult; - - /// Return flags for this backend. - fn flags(&self) -> &Flags; - - /// Get the ISA-dependent flag values that were used to make this trait object. - fn isa_flags(&self) -> Vec; - - /// Return triple for this backend. - fn triple(&self) -> &Triple; - - /// Return name for this backend. - fn name(&self) -> &'static str; - - /// Return the register universe for this backend. - fn reg_universe(&self) -> &RealRegUniverse; - - /// Machine-specific condcode info needed by TargetIsa. - /// Condition that will be true when an IaddIfcout overflows. - fn unsigned_add_overflow_condition(&self) -> IntCC; - - /// Produces unwind info based on backend results. - #[cfg(feature = "unwind")] - fn emit_unwind_info( - &self, - _result: &MachCompileResult, - _kind: UnwindInfoKind, - ) -> CodegenResult> { - // By default, an backend cannot produce unwind info. - Ok(None) - } - - /// Creates a new System V Common Information Entry for the ISA. - #[cfg(feature = "unwind")] - fn create_systemv_cie(&self) -> Option { - // By default, an ISA cannot create a System V CIE - None - } - /// Maps a regalloc::Reg to a DWARF register number. - #[cfg(feature = "unwind")] - fn map_reg_to_dwarf(&self, _: Reg) -> Result { - Err(RegisterMappingError::UnsupportedArchitecture) - } - - /// Returns an object that can be used to build the text section of an - /// executable. - /// - /// This object will internally attempt to handle as many relocations as - /// possible using relative calls/jumps/etc between functions. - /// - /// The `num_labeled_funcs` argument here is the number of functions which - /// will be "labeled" or might have calls between them, typically the number - /// of defined functions in the object file. - fn text_section_builder(&self, num_labeled_funcs: u32) -> Box; -} - /// An object that can be used to create the text section of an executable. /// /// This primarily handles resolving relative relocations at diff --git a/crates/cranelift/src/obj.rs b/crates/cranelift/src/obj.rs index 763ae1afcd..62c7ed9ba0 100644 --- a/crates/cranelift/src/obj.rs +++ b/crates/cranelift/src/obj.rs @@ -205,7 +205,6 @@ impl<'a> ObjectBuilder<'a> { systemv_unwind_info: Vec::new(), relocations: Vec::new(), text: isa - .get_mach_backend() .text_section_builder((module.functions.len() - module.num_imported_funcs) as u32), added_unwind_info: false, }