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Move the initial stack pointer adjustment to after the CSR pushes.

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This commit is contained in:
Tyler McMullen
2017-12-04 16:03:04 -08:00
committed by Jakob Stoklund Olesen
parent ebcbd54f61
commit a75248d2cf
2 changed files with 9 additions and 5 deletions
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6
cranelift/filetests/isa/intel/prologue-epilogue.cton
View File

@@ -4,12 +4,14 @@ set is_compressed
isa intel haswell
function %foo() {
ss0 = local 168
ebb0:
return
}
; check: function %foo(i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] native {
; nextln: ss0 = incoming_arg 48, offset -48
; nextln: ss0 = local 168, offset -216
; nextln: ss1 = incoming_arg 48, offset -48
; check: ebb0(v0: i64 [%rbp], v1: i64 [%rbx], v2: i64 [%r12], v3: i64 [%r13], v4: i64 [%r14], v5: i64 [%r15]):
; nextln: x86_push v0
; nextln: copy_special %rsp -> %rbp
@@ -18,6 +20,8 @@ ebb0:
; nextln: x86_push v3
; nextln: x86_push v4
; nextln: x86_push v5
; nextln: adjust_sp_imm -168
; nextln: adjust_sp_imm 168
; nextln: v11 = x86_pop.i64
; nextln: v10 = x86_pop.i64
; nextln: v9 = x86_pop.i64

8
lib/cretonne/src/isa/intel/abi.rs
View File

@@ -234,10 +234,6 @@ fn insert_prologue(
RU::rbp as RegUnit,
);
if stack_size > 0 {
pos.ins().adjust_sp_imm(Imm64::new(-stack_size));
}
for reg in csrs.iter() {
// Append param to entry EBB
let csr_arg = pos.func.dfg.append_ebb_param(ebb, csr_type);
@@ -248,6 +244,10 @@ fn insert_prologue(
// Remember it so we can push it momentarily
pos.ins().x86_push(csr_arg);
}
if stack_size > 0 {
pos.ins().adjust_sp_imm(Imm64::new(-stack_size));
}
}
/// Find all `return` instructions and insert epilogues before them.