Add an enable_e setting for the RV32E instruction set.

This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.

lib/cretonne/src/isa/riscv/settings.rs

@@ -24,7 +24,8 @@ mod tests {
                     supports_a = false\n\
                     supports_f = false\n\
                     supports_d = false\n\
-                    enable_m = true\n");
+                    enable_m = true\n\
+                    enable_e = false\n");
         // Predicates are not part of the Display output.
         assert_eq!(f.full_float(), false);
     }