Files
wasmtime/lib/cretonne/src/isa/riscv/settings.rs
Jakob Stoklund Olesen a4acc26d5a Add an enable_e setting for the RV32E instruction set.
This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.
2017-04-26 13:50:52 -07:00

52 lines
1.7 KiB
Rust

//! RISC-V Settings.
use settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/cretonne/meta/gen_settings.py`. This file contains a public
// `Flags` struct with an impl for all of the settings defined in
// `lib/cretonne/meta/cretonne/settings.py`.
include!(concat!(env!("OUT_DIR"), "/settings-riscv.rs"));
#[cfg(test)]
mod tests {
use super::{builder, Flags};
use settings::{self, Configurable};
#[test]
fn display_default() {
let shared = settings::Flags::new(&settings::builder());
let b = builder();
let f = Flags::new(&shared, &b);
assert_eq!(f.to_string(),
"[riscv]\n\
supports_m = false\n\
supports_a = false\n\
supports_f = false\n\
supports_d = false\n\
enable_m = true\n\
enable_e = false\n");
// Predicates are not part of the Display output.
assert_eq!(f.full_float(), false);
}
#[test]
fn predicates() {
let shared = settings::Flags::new(&settings::builder());
let mut b = builder();
b.set_bool("supports_f", true).unwrap();
b.set_bool("supports_d", true).unwrap();
let f = Flags::new(&shared, &b);
assert_eq!(f.full_float(), true);
let mut sb = settings::builder();
sb.set_bool("enable_simd", false).unwrap();
let shared = settings::Flags::new(&sb);
let mut b = builder();
b.set_bool("supports_f", true).unwrap();
b.set_bool("supports_d", true).unwrap();
let f = Flags::new(&shared, &b);
assert_eq!(f.full_float(), false);
}
}