Enable more CLIF tests on AArch64

The tests for the SIMD floating-point maximum and minimum operations
require particular care because the handling of the NaN values is
non-deterministic and may vary between platforms. There is no way to
match several NaN values in a test, so the solution is to extract the
non-deterministic test cases into a separate file that is subsequently
replicated for every backend under test, with adjustments made to the
expected results.

Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
2021-07-06 13:22:11 +01:00
parent fb32e49ed7
commit a1b39276e1
78 changed files with 258 additions and 77 deletions

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@@ -1,8 +1,8 @@
; Test basic code generation for control flow WebAssembly instructions.
test compile
target aarch64
target i686 haswell
target x86_64 haswell
function %br_if(i32) -> i32 {

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@@ -1,6 +1,7 @@
; Test code generation for WebAssembly type conversion operators.
test compile
target aarch64
target x86_64 haswell
function %i32_wrap_i64(i64) -> i32 {

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@@ -1,6 +1,7 @@
; Test basic code generation for f32 arithmetic WebAssembly instructions.
test compile
target aarch64
target i686 haswell
target i686 baseline
target x86_64 haswell

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@@ -1,8 +1,8 @@
; Test code generation for WebAssembly f32 comparison operators.
test compile
target aarch64
target i686 haswell
target x86_64 haswell
function %f32_eq(f32, f32) -> i32 {

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@@ -3,6 +3,7 @@ test compile
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
; explicitly mention the pointer width.
target aarch64
target x86_64 haswell
function %f32_load(i32, i64 vmctx) -> f32 {

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@@ -1,6 +1,7 @@
; Test basic code generation for f64 arithmetic WebAssembly instructions.
test compile
target aarch64
target x86_64 haswell
target x86_64 baseline

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@@ -1,8 +1,8 @@
; Test code generation for WebAssembly f64 comparison operators.
test compile
target aarch64
target i686 haswell
target x86_64 haswell
function %f64_eq(f64, f64) -> i32 {

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@@ -3,6 +3,7 @@ test compile
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
; explicitly mention the pointer width.
target aarch64
target x86_64 haswell
function %f64_load(i32, i64 vmctx) -> f64 {

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@@ -1,6 +1,7 @@
; Test basic code generation for i32 arithmetic WebAssembly instructions.
test compile
target aarch64
target i686 haswell
target i686 baseline
target x86_64 haswell

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@@ -1,8 +1,8 @@
; Test code generation for WebAssembly i32 comparison operators.
test compile
target aarch64
target i686 haswell
target x86_64 haswell
function %i32_eqz(i32) -> i32 {

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@@ -3,6 +3,7 @@ test compile
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
; explicitly mention the pointer width.
target aarch64
target x86_64 haswell
function %i32_load(i32, i64 vmctx) -> i32 {

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@@ -1,6 +1,7 @@
; Test basic code generation for i64 arithmetic WebAssembly instructions.
test compile
target aarch64
target x86_64 haswell
target x86_64 baseline

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@@ -1,6 +1,7 @@
; Test code generation for WebAssembly i64 comparison operators.
test compile
target aarch64
target x86_64 haswell
function %i64_eqz(i64) -> i32 {

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@@ -3,6 +3,7 @@ test compile
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
; explicitly mention the pointer width.
target aarch64
target x86_64 haswell
function %i64_load(i32, i64 vmctx) -> i64 {

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@@ -1,4 +1,5 @@
test compile
target aarch64
target x86_64 haswell
;; Returning many mixed values.

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@@ -1,4 +1,5 @@
test compile
target aarch64
target x86_64 haswell
function %returner(i32, i64, f32, f64) -> i32, i64, f32, f64 {

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@@ -4,6 +4,7 @@
test compile
set enable_safepoints=true
target aarch64
target i686 haswell
function %select_ref(i32, r32, r32) -> r32 {

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@@ -4,6 +4,7 @@
test compile
set enable_safepoints=true
target aarch64
target x86_64 haswell
function %select_ref(i32, r64, r64) -> r64 {

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@@ -1,8 +1,8 @@
; Test basic code generation for the select WebAssembly instruction.
test compile
target aarch64
target i686 haswell
target x86_64 haswell
function %select_i32(i32, i32, i32) -> i32 {