diff --git a/cranelift/codegen/meta/src/shared/instructions.rs b/cranelift/codegen/meta/src/shared/instructions.rs
index ffded34f95..2bb8d9a637 100644
--- a/cranelift/codegen/meta/src/shared/instructions.rs
+++ b/cranelift/codegen/meta/src/shared/instructions.rs
@@ -3597,9 +3597,12 @@ pub(crate) fn define(
         Inst::new(
             "fmin",
             r#"
-        Floating point minimum, propagating NaNs.
+        Floating point minimum, propagating NaNs using the WebAssembly rules.
 
-        If either operand is NaN, this returns a NaN.
+        If either operand is NaN, this returns NaN with an unspecified sign. Furthermore, if
+        each input NaN consists of a mantissa whose most significant bit is 1 and the rest is
+        0, then the output has the same form. Otherwise, the output mantissa's most significant
+        bit is 1 and the rest is unspecified.
         "#,
             &formats.binary,
         )
@@ -3629,9 +3632,12 @@ pub(crate) fn define(
         Inst::new(
             "fmax",
             r#"
-        Floating point maximum, propagating NaNs.
+        Floating point maximum, propagating NaNs using the WebAssembly rules.
 
-        If either operand is NaN, this returns a NaN.
+        If either operand is NaN, this returns NaN with an unspecified sign. Furthermore, if
+        each input NaN consists of a mantissa whose most significant bit is 1 and the rest is
+        0, then the output has the same form. Otherwise, the output mantissa's most significant
+        bit is 1 and the rest is unspecified.
         "#,
             &formats.binary,
         )
diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs
index 6e64654568..8dc45061a6 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower.rs
@@ -13,7 +13,7 @@ use crate::ir::Inst as IRInst;
 use crate::ir::{Opcode, Type};
 use crate::machinst::lower::*;
 use crate::machinst::*;
-use crate::CodegenResult;
+use crate::{CodegenError, CodegenResult};
 
 use crate::isa::aarch64::inst::*;
 use crate::isa::aarch64::AArch64Backend;
@@ -1103,50 +1103,96 @@ pub(crate) fn lower_vector_compare<C: LowerCtx<I = Inst>>(
         _ => false,
     };
     let size = VectorSize::from_ty(ty);
-    // 'Less than' operations are implemented by swapping
-    // the order of operands and using the 'greater than'
-    // instructions.
-    // 'Not equal' is implemented with 'equal' and inverting
-    // the result.
-    let (alu_op, swap) = match (is_float, cond) {
-        (false, Cond::Eq) => (VecALUOp::Cmeq, false),
-        (false, Cond::Ne) => (VecALUOp::Cmeq, false),
-        (false, Cond::Ge) => (VecALUOp::Cmge, false),
-        (false, Cond::Gt) => (VecALUOp::Cmgt, false),
-        (false, Cond::Le) => (VecALUOp::Cmge, true),
-        (false, Cond::Lt) => (VecALUOp::Cmgt, true),
-        (false, Cond::Hs) => (VecALUOp::Cmhs, false),
-        (false, Cond::Hi) => (VecALUOp::Cmhi, false),
-        (false, Cond::Ls) => (VecALUOp::Cmhs, true),
-        (false, Cond::Lo) => (VecALUOp::Cmhi, true),
-        (true, Cond::Eq) => (VecALUOp::Fcmeq, false),
-        (true, Cond::Ne) => (VecALUOp::Fcmeq, false),
-        (true, Cond::Mi) => (VecALUOp::Fcmgt, true),
-        (true, Cond::Ls) => (VecALUOp::Fcmge, true),
-        (true, Cond::Ge) => (VecALUOp::Fcmge, false),
-        (true, Cond::Gt) => (VecALUOp::Fcmgt, false),
-        _ => unreachable!(),
-    };
 
-    if swap {
-        std::mem::swap(&mut rn, &mut rm);
-    }
+    if is_float && (cond == Cond::Vc || cond == Cond::Vs) {
+        let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
 
-    ctx.emit(Inst::VecRRR {
-        alu_op,
-        rd,
-        rn,
-        rm,
-        size,
-    });
-
-    if cond == Cond::Ne {
-        ctx.emit(Inst::VecMisc {
-            op: VecMisc2::Not,
+        ctx.emit(Inst::VecRRR {
+            alu_op: VecALUOp::Fcmeq,
             rd,
-            rn: rd.to_reg(),
+            rn,
+            rm: rn,
             size,
         });
+        ctx.emit(Inst::VecRRR {
+            alu_op: VecALUOp::Fcmeq,
+            rd: tmp,
+            rn: rm,
+            rm,
+            size,
+        });
+        ctx.emit(Inst::VecRRR {
+            alu_op: VecALUOp::And,
+            rd,
+            rn: rd.to_reg(),
+            rm: tmp.to_reg(),
+            size,
+        });
+
+        if cond == Cond::Vs {
+            ctx.emit(Inst::VecMisc {
+                op: VecMisc2::Not,
+                rd,
+                rn: rd.to_reg(),
+                size,
+            });
+        }
+    } else {
+        // 'Less than' operations are implemented by swapping
+        // the order of operands and using the 'greater than'
+        // instructions.
+        // 'Not equal' is implemented with 'equal' and inverting
+        // the result.
+        let (alu_op, swap) = match (is_float, cond) {
+            (false, Cond::Eq) => (VecALUOp::Cmeq, false),
+            (false, Cond::Ne) => (VecALUOp::Cmeq, false),
+            (false, Cond::Ge) => (VecALUOp::Cmge, false),
+            (false, Cond::Gt) => (VecALUOp::Cmgt, false),
+            (false, Cond::Le) => (VecALUOp::Cmge, true),
+            (false, Cond::Lt) => (VecALUOp::Cmgt, true),
+            (false, Cond::Hs) => (VecALUOp::Cmhs, false),
+            (false, Cond::Hi) => (VecALUOp::Cmhi, false),
+            (false, Cond::Ls) => (VecALUOp::Cmhs, true),
+            (false, Cond::Lo) => (VecALUOp::Cmhi, true),
+            (true, Cond::Eq) => (VecALUOp::Fcmeq, false),
+            (true, Cond::Ne) => (VecALUOp::Fcmeq, false),
+            (true, Cond::Mi) => (VecALUOp::Fcmgt, true),
+            (true, Cond::Ls) => (VecALUOp::Fcmge, true),
+            (true, Cond::Ge) => (VecALUOp::Fcmge, false),
+            (true, Cond::Gt) => (VecALUOp::Fcmgt, false),
+            _ => {
+                return Err(CodegenError::Unsupported(format!(
+                    "Unsupported {} SIMD vector comparison: {:?}",
+                    if is_float {
+                        "floating-point"
+                    } else {
+                        "integer"
+                    },
+                    cond
+                )))
+            }
+        };
+
+        if swap {
+            std::mem::swap(&mut rn, &mut rm);
+        }
+
+        ctx.emit(Inst::VecRRR {
+            alu_op,
+            rd,
+            rn,
+            rm,
+            size,
+        });
+
+        if cond == Cond::Ne {
+            ctx.emit(Inst::VecMisc {
+                op: VecMisc2::Not,
+                rd,
+                rn: rd.to_reg(),
+                size,
+            });
+        }
     }
 
     Ok(())
diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
index 3ddc3712a0..4c8d64b1c1 100644
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1803,23 +1803,30 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         }
 
         Opcode::Bint => {
+            let ty = ty.unwrap();
+
+            if ty.is_vector() {
+                return Err(CodegenError::Unsupported(format!(
+                    "Bint: Unsupported type: {:?}",
+                    ty
+                )));
+            }
+
             // Booleans are stored as all-zeroes (0) or all-ones (-1). We AND
             // out the LSB to give a 0 / 1-valued integer result.
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let output_bits = ty_bits(ctx.output_ty(insn, 0));
+            let input = put_input_in_regs(ctx, inputs[0]);
+            let output = get_output_reg(ctx, outputs[0]);
 
-            let (imm_ty, alu_op) = if output_bits > 32 {
-                (I64, ALUOp::And64)
-            } else {
-                (I32, ALUOp::And32)
-            };
             ctx.emit(Inst::AluRRImmLogic {
-                alu_op,
-                rd,
-                rn,
-                imml: ImmLogic::maybe_from_u64(1, imm_ty).unwrap(),
+                alu_op: ALUOp::And32,
+                rd: output.regs()[0],
+                rn: input.regs()[0],
+                imml: ImmLogic::maybe_from_u64(1, I32).unwrap(),
             });
+
+            if ty_bits(ty) > 64 {
+                lower_constant_u64(ctx, output.regs()[1], 0);
+            }
         }
 
         Opcode::Bitcast => {
@@ -2240,7 +2247,9 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             }
         }
 
-        Opcode::VallTrue if ctx.input_ty(insn, 0) == I64X2 => {
+        Opcode::VallTrue if ty_bits(ctx.input_ty(insn, 0).lane_type()) == 64 => {
+            debug_assert!(ctx.input_ty(insn, 0).is_vector());
+
             let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
             let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
             let tmp = ctx.alloc_tmp(I64X2).only_reg().unwrap();
diff --git a/cranelift/filetests/filetests/legalizer/bxor_imm.clif b/cranelift/filetests/filetests/legalizer/bxor_imm.clif
index bf959a7364..12a149eed9 100644
--- a/cranelift/filetests/filetests/legalizer/bxor_imm.clif
+++ b/cranelift/filetests/filetests/legalizer/bxor_imm.clif
@@ -1,4 +1,5 @@
 test legalizer
+target aarch64
 target x86_64
 
 function %foo(i64, i64) -> i64 {
diff --git a/cranelift/filetests/filetests/legalizer/iconst-i64.clif b/cranelift/filetests/filetests/legalizer/iconst-i64.clif
index 6aa7361b45..359ca772e9 100644
--- a/cranelift/filetests/filetests/legalizer/iconst-i64.clif
+++ b/cranelift/filetests/filetests/legalizer/iconst-i64.clif
@@ -1,4 +1,5 @@
 test legalizer
+target aarch64
 target i686
 
 function %foo() -> i64 {
diff --git a/cranelift/filetests/filetests/legalizer/isplit-bb.clif b/cranelift/filetests/filetests/legalizer/isplit-bb.clif
index 7e55eb1eb9..38b0755c00 100644
--- a/cranelift/filetests/filetests/legalizer/isplit-bb.clif
+++ b/cranelift/filetests/filetests/legalizer/isplit-bb.clif
@@ -1,4 +1,5 @@
 test legalizer
+target aarch64
 target x86_64
 
 function u0:0(i128, i128, i64) -> i128 system_v {
diff --git a/cranelift/filetests/filetests/licm/br-table.clif b/cranelift/filetests/filetests/licm/br-table.clif
index 61ac789021..8e2f042558 100644
--- a/cranelift/filetests/filetests/licm/br-table.clif
+++ b/cranelift/filetests/filetests/licm/br-table.clif
@@ -1,5 +1,6 @@
 test compile
 set opt_level=speed_and_size
+target aarch64
 target x86_64
 
 function %br_table_opt() {
@@ -9,7 +10,7 @@ function %br_table_opt() {
         v0 = iconst.i32 1
         br_table v0, block2, jt0
 
-    block1: 
+    block1:
         return
 
     block2:
diff --git a/cranelift/filetests/filetests/licm/jump-table-entry.clif b/cranelift/filetests/filetests/licm/jump-table-entry.clif
index 6f754185a5..66b8f9817c 100644
--- a/cranelift/filetests/filetests/licm/jump-table-entry.clif
+++ b/cranelift/filetests/filetests/licm/jump-table-entry.clif
@@ -1,4 +1,5 @@
 test licm
+target aarch64
 target x86_64
 
 function %dont_hoist_jump_table_entry_during_licm() {
diff --git a/cranelift/filetests/filetests/licm/load_readonly_notrap.clif b/cranelift/filetests/filetests/licm/load_readonly_notrap.clif
index f663646b9e..011b5833d5 100644
--- a/cranelift/filetests/filetests/licm/load_readonly_notrap.clif
+++ b/cranelift/filetests/filetests/licm/load_readonly_notrap.clif
@@ -1,5 +1,6 @@
 test licm
 
+target aarch64
 target x86_64
 
 ;; Nontrapping readonly load from address that is not loop-dependent
diff --git a/cranelift/filetests/filetests/licm/reject_load_notrap.clif b/cranelift/filetests/filetests/licm/reject_load_notrap.clif
index 58f046357d..6236d0d1ef 100644
--- a/cranelift/filetests/filetests/licm/reject_load_notrap.clif
+++ b/cranelift/filetests/filetests/licm/reject_load_notrap.clif
@@ -1,5 +1,6 @@
 test licm
 
+target aarch64
 target x86_64
 
 ;; Nontrapping possibly-not-readonly load from address that is not
diff --git a/cranelift/filetests/filetests/licm/reject_load_readonly.clif b/cranelift/filetests/filetests/licm/reject_load_readonly.clif
index f794bad6b0..c94ace2591 100644
--- a/cranelift/filetests/filetests/licm/reject_load_readonly.clif
+++ b/cranelift/filetests/filetests/licm/reject_load_readonly.clif
@@ -1,5 +1,6 @@
 test licm
 
+target aarch64
 target x86_64
 
 ;; Maybe-trapping readonly load from address that is not
diff --git a/cranelift/filetests/filetests/peepmatic/branch.clif b/cranelift/filetests/filetests/peepmatic/branch.clif
index 0f68bbe9cb..3e12cbcc6d 100644
--- a/cranelift/filetests/filetests/peepmatic/branch.clif
+++ b/cranelift/filetests/filetests/peepmatic/branch.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 function %icmp_to_brz_fold(i32) -> i32 {
diff --git a/cranelift/filetests/filetests/peepmatic/div_by_const_indirect.clif b/cranelift/filetests/filetests/peepmatic/div_by_const_indirect.clif
index ba65b2418c..12c5f29d2a 100644
--- a/cranelift/filetests/filetests/peepmatic/div_by_const_indirect.clif
+++ b/cranelift/filetests/filetests/peepmatic/div_by_const_indirect.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64 baseline
 
 ; Cases where the denominator is created by an iconst
diff --git a/cranelift/filetests/filetests/peepmatic/div_by_const_non_power_of_2.clif b/cranelift/filetests/filetests/peepmatic/div_by_const_non_power_of_2.clif
index 0759f92ca9..3731f7fdc7 100644
--- a/cranelift/filetests/filetests/peepmatic/div_by_const_non_power_of_2.clif
+++ b/cranelift/filetests/filetests/peepmatic/div_by_const_non_power_of_2.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/peepmatic/div_by_const_power_of_2.clif b/cranelift/filetests/filetests/peepmatic/div_by_const_power_of_2.clif
index a2110a5a75..c91c15468c 100644
--- a/cranelift/filetests/filetests/peepmatic/div_by_const_power_of_2.clif
+++ b/cranelift/filetests/filetests/peepmatic/div_by_const_power_of_2.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/peepmatic/do_not_keep_applying_optimizations_after_replacing_with_an_alias.clif b/cranelift/filetests/filetests/peepmatic/do_not_keep_applying_optimizations_after_replacing_with_an_alias.clif
index cc24167267..f3fc4c72a9 100644
--- a/cranelift/filetests/filetests/peepmatic/do_not_keep_applying_optimizations_after_replacing_with_an_alias.clif
+++ b/cranelift/filetests/filetests/peepmatic/do_not_keep_applying_optimizations_after_replacing_with_an_alias.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 ;; This file used to trigger assertions where we would keep trying to
diff --git a/cranelift/filetests/filetests/peepmatic/do_not_reorder_instructions_when_transplanting.clif b/cranelift/filetests/filetests/peepmatic/do_not_reorder_instructions_when_transplanting.clif
index 7fc95f0fdb..37f7652831 100644
--- a/cranelift/filetests/filetests/peepmatic/do_not_reorder_instructions_when_transplanting.clif
+++ b/cranelift/filetests/filetests/peepmatic/do_not_reorder_instructions_when_transplanting.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 ;; Test that although v5 can be replaced with v1, we don't transplant `load.i32
diff --git a/cranelift/filetests/filetests/peepmatic/fold-extended-move-wraparound.clif b/cranelift/filetests/filetests/peepmatic/fold-extended-move-wraparound.clif
index e48b91a4b1..f6db2cfbad 100644
--- a/cranelift/filetests/filetests/peepmatic/fold-extended-move-wraparound.clif
+++ b/cranelift/filetests/filetests/peepmatic/fold-extended-move-wraparound.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 function %wraparound(i64 vmctx) -> f32 system_v {
diff --git a/cranelift/filetests/filetests/peepmatic/rem_by_const_non_power_of_2.clif b/cranelift/filetests/filetests/peepmatic/rem_by_const_non_power_of_2.clif
index 7df5baf4e3..dd13e73c0f 100644
--- a/cranelift/filetests/filetests/peepmatic/rem_by_const_non_power_of_2.clif
+++ b/cranelift/filetests/filetests/peepmatic/rem_by_const_non_power_of_2.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/peepmatic/rem_by_const_power_of_2.clif b/cranelift/filetests/filetests/peepmatic/rem_by_const_power_of_2.clif
index c795b73c19..23225a4ec9 100644
--- a/cranelift/filetests/filetests/peepmatic/rem_by_const_power_of_2.clif
+++ b/cranelift/filetests/filetests/peepmatic/rem_by_const_power_of_2.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/peepmatic/replace_branching_instructions_and_cfg_predecessors.clif b/cranelift/filetests/filetests/peepmatic/replace_branching_instructions_and_cfg_predecessors.clif
index 17ca472b7e..643f08a4a7 100644
--- a/cranelift/filetests/filetests/peepmatic/replace_branching_instructions_and_cfg_predecessors.clif
+++ b/cranelift/filetests/filetests/peepmatic/replace_branching_instructions_and_cfg_predecessors.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 function u0:2(i64 , i64) {
diff --git a/cranelift/filetests/filetests/peepmatic/simplify32.clif b/cranelift/filetests/filetests/peepmatic/simplify32.clif
index b1c6786a05..95ba29f30a 100644
--- a/cranelift/filetests/filetests/peepmatic/simplify32.clif
+++ b/cranelift/filetests/filetests/peepmatic/simplify32.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target i686
 
 ;; 32-bits platforms.
diff --git a/cranelift/filetests/filetests/peepmatic/simplify64.clif b/cranelift/filetests/filetests/peepmatic/simplify64.clif
index 93c289ccdd..4fb5b81e18 100644
--- a/cranelift/filetests/filetests/peepmatic/simplify64.clif
+++ b/cranelift/filetests/filetests/peepmatic/simplify64.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 ;; 64-bits platforms.
diff --git a/cranelift/filetests/filetests/peepmatic/simplify_instruction_into_alias_of_value.clif b/cranelift/filetests/filetests/peepmatic/simplify_instruction_into_alias_of_value.clif
index 3000369bb5..bb21ec2553 100644
--- a/cranelift/filetests/filetests/peepmatic/simplify_instruction_into_alias_of_value.clif
+++ b/cranelift/filetests/filetests/peepmatic/simplify_instruction_into_alias_of_value.clif
@@ -1,4 +1,5 @@
 test peepmatic
+target aarch64
 target x86_64
 
 ;; The `isub` is a no-op, but we can't replace the whole `isub` instruction with
diff --git a/cranelift/filetests/filetests/postopt/basic.clif b/cranelift/filetests/filetests/postopt/basic.clif
index 7b4c07b422..55a8d03738 100644
--- a/cranelift/filetests/filetests/postopt/basic.clif
+++ b/cranelift/filetests/filetests/postopt/basic.clif
@@ -1,4 +1,5 @@
 test postopt
+target aarch64
 target i686 legacy
 
 ; Test that compare+branch sequences are folded effectively on x86.
diff --git a/cranelift/filetests/filetests/preopt/branch.clif b/cranelift/filetests/filetests/preopt/branch.clif
index 50274c4890..dc6f0acee2 100644
--- a/cranelift/filetests/filetests/preopt/branch.clif
+++ b/cranelift/filetests/filetests/preopt/branch.clif
@@ -1,4 +1,5 @@
 test preopt
+target aarch64
 target x86_64
 
 function %brz_fold() -> i32 {
diff --git a/cranelift/filetests/filetests/preopt/constant_fold.clif b/cranelift/filetests/filetests/preopt/constant_fold.clif
index e2cc3e4562..6d90187199 100644
--- a/cranelift/filetests/filetests/preopt/constant_fold.clif
+++ b/cranelift/filetests/filetests/preopt/constant_fold.clif
@@ -1,4 +1,5 @@
 test preopt
+target aarch64
 target x86_64
 
 function %constant_fold(f64) -> f64 {
diff --git a/cranelift/filetests/filetests/preopt/numerical.clif b/cranelift/filetests/filetests/preopt/numerical.clif
index 044a3df6a0..6ab642a550 100644
--- a/cranelift/filetests/filetests/preopt/numerical.clif
+++ b/cranelift/filetests/filetests/preopt/numerical.clif
@@ -1,4 +1,5 @@
 test preopt
+target aarch64
 target x86_64
 
 function %iadd_fold() -> i32 {
@@ -33,4 +34,4 @@ block0:
 ; nextln:     v1 = iconst.i32 1
 ; nextln:     v2 = iconst.i32 41
 ; nextln:     return v2
-; nextln: }
\ No newline at end of file
+; nextln: }
diff --git a/cranelift/filetests/filetests/regress/allow-relaxation-shrink.clif b/cranelift/filetests/filetests/regress/allow-relaxation-shrink.clif
index 5d4a37f5e6..fd95cc2f4c 100644
--- a/cranelift/filetests/filetests/regress/allow-relaxation-shrink.clif
+++ b/cranelift/filetests/filetests/regress/allow-relaxation-shrink.clif
@@ -1,4 +1,5 @@
 test compile
+target aarch64
 target x86_64 legacy
 
 ; This checks that code shrink is allowed while relaxing code, when code shrink
diff --git a/cranelift/filetests/filetests/runtests/i128-bint.clif b/cranelift/filetests/filetests/runtests/i128-bint.clif
index 3f51febe64..4c0ed4f890 100644
--- a/cranelift/filetests/filetests/runtests/i128-bint.clif
+++ b/cranelift/filetests/filetests/runtests/i128-bint.clif
@@ -1,4 +1,5 @@
 test run
+target aarch64
 target x86_64 machinst
 
 function %bint_b8_i128() -> i64, i64 {
diff --git a/cranelift/filetests/filetests/runtests/i128-bitrev.clif b/cranelift/filetests/filetests/runtests/i128-bitrev.clif
index 60264dca7d..e494b32597 100644
--- a/cranelift/filetests/filetests/runtests/i128-bitrev.clif
+++ b/cranelift/filetests/filetests/runtests/i128-bitrev.clif
@@ -1,4 +1,5 @@
 test run
+target aarch64
 target x86_64 machinst
 target x86_64 legacy
 
diff --git a/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-aarch64.clif b/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-aarch64.clif
new file mode 100644
index 0000000000..f657d1e533
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-aarch64.clif
@@ -0,0 +1,23 @@
+; Test the non-deterministic aspects of the SIMD arithmetic operations.
+; If you change this file, you should most likely update
+; simd-arithmetic-nondeterministic*.clif as well.
+test run
+target aarch64
+
+function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
+block0(v0: f64x2, v1: f64x2):
+    v2 = fmax v0, v1
+    return v2
+}
+
+; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN:0x42 0.0]
+
+function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
+block0(v0: f64x2, v1: f64x2):
+    v2 = fmin v0, v1
+    return v2
+}
+
+; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN NaN]
+; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [NaN 0.0]
+; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN:0x42 0.0]
diff --git a/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-x86_64.clif b/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-x86_64.clif
new file mode 100644
index 0000000000..323579b6ce
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/simd-arithmetic-nondeterministic-x86_64.clif
@@ -0,0 +1,28 @@
+; Test the non-deterministic aspects of the SIMD arithmetic operations.
+; If you change this file, you should most likely update
+; simd-arithmetic-nondeterministic*.clif as well.
+test run
+set enable_simd
+target x86_64 machinst skylake
+
+function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
+block0(v0: f64x2, v1: f64x2):
+    v2 = fmax v0, v1
+    return v2
+}
+
+; note below how NaNs are quieted but (unlike fmin), retain their sign: this discrepancy is allowed by non-determinism
+; in the spec, see https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
+; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN 0.0]
+
+function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
+block0(v0: f64x2, v1: f64x2):
+    v2 = fmin v0, v1
+    return v2
+}
+
+; note below how NaNs are quieted and negative: this is due to non-determinism in the spec for NaNs, see
+; https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
+; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN -NaN]
+; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [-NaN 0.0]
+; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [-NaN 0.0]
diff --git a/cranelift/filetests/filetests/runtests/simd-arithmetic.clif b/cranelift/filetests/filetests/runtests/simd-arithmetic.clif
index f59488ee0c..5397f5d874 100644
--- a/cranelift/filetests/filetests/runtests/simd-arithmetic.clif
+++ b/cranelift/filetests/filetests/runtests/simd-arithmetic.clif
@@ -1,5 +1,5 @@
 test run
-; target aarch64 TODO: Not yet implemented on aarch64
+target aarch64
 ; target s390x TODO: Not yet implemented on s390x
 set enable_simd
 target x86_64 machinst skylake
@@ -125,7 +125,7 @@ block0:
 ; run
 
 function %sqrt_f64x2(f64x2) -> f64x2 {
-block0(v0: f64x2): 
+block0(v0: f64x2):
     v1 = sqrt v0
     return v1
 }
@@ -136,26 +136,22 @@ block0(v0: f64x2, v1: f64x2):
     v2 = fmax v0, v1
     return v2
 }
-; note below how NaNs are quieted but (unlike fmin), retain their sign: this discrepancy is allowed by non-determinism
-; in the spec, see https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
+; This operation exhibits non-deterministic behaviour for some input NaN values;
+; refer to the simd-arithmetic-nondeterministic*.clif files for the respective tests.
 ; run: %fmax_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [+0x0.0 0x1.0]
 ; run: %fmax_f64x2([-NaN NaN], [0x0.0 0x100.0]) == [-NaN NaN]
 ; run: %fmax_f64x2([NaN 0.0], [0.0 0.0]) == [NaN 0.0]
 ; run: %fmax_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
-; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN 0.0]
 
 function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
 block0(v0: f64x2, v1: f64x2):
     v2 = fmin v0, v1
     return v2
 }
-; note below how NaNs are quieted and negative: this is due to non-determinism in the spec for NaNs, see
-; https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
+; This operation exhibits non-deterministic behaviour for some input NaN values;
+; refer to the simd-arithmetic-nondeterministic*.clif files for the respective tests.
 ; run: %fmin_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [-0x0.0 -0x1.0]
-; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN -NaN]
-; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [-NaN 0.0]
 ; run: %fmin_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
-; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [-NaN 0.0]
 
 function %fneg_f64x2(f64x2) -> f64x2 {
 block0(v0: f64x2):
diff --git a/cranelift/filetests/filetests/runtests/simd-bitwise-run.clif b/cranelift/filetests/filetests/runtests/simd-bitwise-run.clif
index 0b9d07663c..4f66e51ec4 100644
--- a/cranelift/filetests/filetests/runtests/simd-bitwise-run.clif
+++ b/cranelift/filetests/filetests/runtests/simd-bitwise-run.clif
@@ -1,5 +1,6 @@
 test run
 set enable_simd
+target aarch64
 target x86_64 legacy skylake
 
 ; TODO: once available, replace all lane extraction with `icmp + all_ones`
diff --git a/cranelift/filetests/filetests/runtests/simd-comparison.clif b/cranelift/filetests/filetests/runtests/simd-comparison.clif
index 037466d8d4..33402b1175 100644
--- a/cranelift/filetests/filetests/runtests/simd-comparison.clif
+++ b/cranelift/filetests/filetests/runtests/simd-comparison.clif
@@ -1,5 +1,5 @@
 test run
-; target aarch64 TODO: Not yet implemented on aarch64
+target aarch64
 ; target s390x TODO: Not yet implemented on s390x
 set enable_simd
 target x86_64 machinst
diff --git a/cranelift/filetests/filetests/runtests/simd-lane-access.clif b/cranelift/filetests/filetests/runtests/simd-lane-access.clif
index 7dc1a8a08f..4ab67d9177 100644
--- a/cranelift/filetests/filetests/runtests/simd-lane-access.clif
+++ b/cranelift/filetests/filetests/runtests/simd-lane-access.clif
@@ -1,5 +1,5 @@
 test run
-; target aarch64 TODO: Not yet implemented on aarch64
+target aarch64
 ; target s390x TODO: Not yet implemented on s390x
 set enable_simd
 target x86_64 machinst
diff --git a/cranelift/filetests/filetests/runtests/simd-vconst.clif b/cranelift/filetests/filetests/runtests/simd-vconst.clif
index 7fbbf162a9..49b89a0330 100644
--- a/cranelift/filetests/filetests/runtests/simd-vconst.clif
+++ b/cranelift/filetests/filetests/runtests/simd-vconst.clif
@@ -1,6 +1,6 @@
 test run
 ; target s390x TODO: Not yet implemented on s390x
-; target aarch64 TODO: Not yet implemented on aarch64
+target aarch64
 set enable_simd
 target x86_64 machinst
 set enable_simd
diff --git a/cranelift/filetests/filetests/simple_gvn/readonly.clif b/cranelift/filetests/filetests/simple_gvn/readonly.clif
index 802396f4f8..93ede4a5b8 100644
--- a/cranelift/filetests/filetests/simple_gvn/readonly.clif
+++ b/cranelift/filetests/filetests/simple_gvn/readonly.clif
@@ -1,5 +1,6 @@
 test simple-gvn
 
+target aarch64
 target x86_64
 
 function %eliminate_redundant_global_loads(i32, i64 vmctx) {
diff --git a/cranelift/filetests/filetests/simple_preopt/bitselect.clif b/cranelift/filetests/filetests/simple_preopt/bitselect.clif
index 684d91ee31..97fe62a9f0 100644
--- a/cranelift/filetests/filetests/simple_preopt/bitselect.clif
+++ b/cranelift/filetests/filetests/simple_preopt/bitselect.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 ;; Test replacement of bitselect with vselect for special masks
diff --git a/cranelift/filetests/filetests/simple_preopt/branch.clif b/cranelift/filetests/filetests/simple_preopt/branch.clif
index 21cc7afda3..7bb0cc0452 100644
--- a/cranelift/filetests/filetests/simple_preopt/branch.clif
+++ b/cranelift/filetests/filetests/simple_preopt/branch.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 function %icmp_to_brz_fold(i32) -> i32 {
diff --git a/cranelift/filetests/filetests/simple_preopt/div_by_const_indirect.clif b/cranelift/filetests/filetests/simple_preopt/div_by_const_indirect.clif
index 101e4eb201..7b09c24d04 100644
--- a/cranelift/filetests/filetests/simple_preopt/div_by_const_indirect.clif
+++ b/cranelift/filetests/filetests/simple_preopt/div_by_const_indirect.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64 baseline
 
 ; Cases where the denominator is created by an iconst
diff --git a/cranelift/filetests/filetests/simple_preopt/div_by_const_non_power_of_2.clif b/cranelift/filetests/filetests/simple_preopt/div_by_const_non_power_of_2.clif
index b1225a28d5..f225777718 100644
--- a/cranelift/filetests/filetests/simple_preopt/div_by_const_non_power_of_2.clif
+++ b/cranelift/filetests/filetests/simple_preopt/div_by_const_non_power_of_2.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/simple_preopt/div_by_const_power_of_2.clif b/cranelift/filetests/filetests/simple_preopt/div_by_const_power_of_2.clif
index 83e9f95c8a..09e0aa180c 100644
--- a/cranelift/filetests/filetests/simple_preopt/div_by_const_power_of_2.clif
+++ b/cranelift/filetests/filetests/simple_preopt/div_by_const_power_of_2.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/simple_preopt/do_not_reorder_instructions_when_transplanting.clif b/cranelift/filetests/filetests/simple_preopt/do_not_reorder_instructions_when_transplanting.clif
index a1e9f47f5a..90517d2288 100644
--- a/cranelift/filetests/filetests/simple_preopt/do_not_reorder_instructions_when_transplanting.clif
+++ b/cranelift/filetests/filetests/simple_preopt/do_not_reorder_instructions_when_transplanting.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 ;; Test that although v5 can be replaced with v1, we don't transplant `load.i32
diff --git a/cranelift/filetests/filetests/simple_preopt/fold-extended-move-wraparound.clif b/cranelift/filetests/filetests/simple_preopt/fold-extended-move-wraparound.clif
index 44342481b8..13d77d7cfa 100644
--- a/cranelift/filetests/filetests/simple_preopt/fold-extended-move-wraparound.clif
+++ b/cranelift/filetests/filetests/simple_preopt/fold-extended-move-wraparound.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 function %wraparound(i64 vmctx) -> f32 system_v {
diff --git a/cranelift/filetests/filetests/simple_preopt/rem_by_const_non_power_of_2.clif b/cranelift/filetests/filetests/simple_preopt/rem_by_const_non_power_of_2.clif
index 00d0d9f16e..a7cd49246e 100644
--- a/cranelift/filetests/filetests/simple_preopt/rem_by_const_non_power_of_2.clif
+++ b/cranelift/filetests/filetests/simple_preopt/rem_by_const_non_power_of_2.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/simple_preopt/rem_by_const_power_of_2.clif b/cranelift/filetests/filetests/simple_preopt/rem_by_const_power_of_2.clif
index 1fe085e37c..19cc5e82b5 100644
--- a/cranelift/filetests/filetests/simple_preopt/rem_by_const_power_of_2.clif
+++ b/cranelift/filetests/filetests/simple_preopt/rem_by_const_power_of_2.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target i686 baseline
 
 ; -------- U32 --------
diff --git a/cranelift/filetests/filetests/simple_preopt/replace_branching_instructions_and_cfg_predecessors.clif b/cranelift/filetests/filetests/simple_preopt/replace_branching_instructions_and_cfg_predecessors.clif
index 702896c22d..a6cc0d9fb1 100644
--- a/cranelift/filetests/filetests/simple_preopt/replace_branching_instructions_and_cfg_predecessors.clif
+++ b/cranelift/filetests/filetests/simple_preopt/replace_branching_instructions_and_cfg_predecessors.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 function u0:2(i64 , i64) {
diff --git a/cranelift/filetests/filetests/simple_preopt/sign_extend.clif b/cranelift/filetests/filetests/simple_preopt/sign_extend.clif
index 5bff7f588f..b10b9a2d93 100644
--- a/cranelift/filetests/filetests/simple_preopt/sign_extend.clif
+++ b/cranelift/filetests/filetests/simple_preopt/sign_extend.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 ;; Tests for sign-extending immediates.
diff --git a/cranelift/filetests/filetests/simple_preopt/simplify32.clif b/cranelift/filetests/filetests/simple_preopt/simplify32.clif
index 2582fd69aa..32566cea8b 100644
--- a/cranelift/filetests/filetests/simple_preopt/simplify32.clif
+++ b/cranelift/filetests/filetests/simple_preopt/simplify32.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target i686
 
 ;; 32-bits platforms.
diff --git a/cranelift/filetests/filetests/simple_preopt/simplify64.clif b/cranelift/filetests/filetests/simple_preopt/simplify64.clif
index 4ceabdc335..102746e971 100644
--- a/cranelift/filetests/filetests/simple_preopt/simplify64.clif
+++ b/cranelift/filetests/filetests/simple_preopt/simplify64.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 ;; 64-bits platforms.
diff --git a/cranelift/filetests/filetests/simple_preopt/simplify_instruction_into_alias_of_value.clif b/cranelift/filetests/filetests/simple_preopt/simplify_instruction_into_alias_of_value.clif
index 076d7b17b5..5d10588da3 100644
--- a/cranelift/filetests/filetests/simple_preopt/simplify_instruction_into_alias_of_value.clif
+++ b/cranelift/filetests/filetests/simple_preopt/simplify_instruction_into_alias_of_value.clif
@@ -1,4 +1,5 @@
 test simple_preopt
+target aarch64
 target x86_64
 
 ;; The `isub` is a no-op, but we can't replace the whole `isub` instruction with
diff --git a/cranelift/filetests/filetests/verifier/flags.clif b/cranelift/filetests/filetests/verifier/flags.clif
index dc370c58cb..088523d24a 100644
--- a/cranelift/filetests/filetests/verifier/flags.clif
+++ b/cranelift/filetests/filetests/verifier/flags.clif
@@ -1,4 +1,5 @@
 test verifier
+target aarch64
 target i686
 
 ; Simple, correct use of CPU flags.
diff --git a/cranelift/filetests/filetests/verifier/scalar-to-vector.clif b/cranelift/filetests/filetests/verifier/scalar-to-vector.clif
index 1d04db9957..a955e55a68 100644
--- a/cranelift/filetests/filetests/verifier/scalar-to-vector.clif
+++ b/cranelift/filetests/filetests/verifier/scalar-to-vector.clif
@@ -1,5 +1,6 @@
 test verifier
 set enable_simd=true
+target aarch64
 target x86_64
 
 function %scalar_to_vector() {
diff --git a/cranelift/filetests/filetests/verifier/simd-lane-index.clif b/cranelift/filetests/filetests/verifier/simd-lane-index.clif
index b8051a6b5a..99e04871f4 100644
--- a/cranelift/filetests/filetests/verifier/simd-lane-index.clif
+++ b/cranelift/filetests/filetests/verifier/simd-lane-index.clif
@@ -1,5 +1,6 @@
 test verifier
 set enable_simd
+target aarch64
 target x86_64
 
 function %insertlane_i32x4() {
diff --git a/cranelift/filetests/filetests/wasm/control.clif b/cranelift/filetests/filetests/wasm/control.clif
index 4f40ddffb9..08fc29c0b7 100644
--- a/cranelift/filetests/filetests/wasm/control.clif
+++ b/cranelift/filetests/filetests/wasm/control.clif
@@ -1,8 +1,8 @@
 ; Test basic code generation for control flow WebAssembly instructions.
 test compile
 
+target aarch64
 target i686 haswell
-
 target x86_64 haswell
 
 function %br_if(i32) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/conversions.clif b/cranelift/filetests/filetests/wasm/conversions.clif
index 33602166b4..7b2e2c5aaa 100644
--- a/cranelift/filetests/filetests/wasm/conversions.clif
+++ b/cranelift/filetests/filetests/wasm/conversions.clif
@@ -1,6 +1,7 @@
 ; Test code generation for WebAssembly type conversion operators.
 test compile
 
+target aarch64
 target x86_64 haswell
 
 function %i32_wrap_i64(i64) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/f32-arith.clif b/cranelift/filetests/filetests/wasm/f32-arith.clif
index b7a83f5434..365c4d9d23 100644
--- a/cranelift/filetests/filetests/wasm/f32-arith.clif
+++ b/cranelift/filetests/filetests/wasm/f32-arith.clif
@@ -1,6 +1,7 @@
 ; Test basic code generation for f32 arithmetic WebAssembly instructions.
 test compile
 
+target aarch64
 target i686 haswell
 target i686 baseline
 target x86_64 haswell
diff --git a/cranelift/filetests/filetests/wasm/f32-compares.clif b/cranelift/filetests/filetests/wasm/f32-compares.clif
index e569a94821..ad1bf6ad7e 100644
--- a/cranelift/filetests/filetests/wasm/f32-compares.clif
+++ b/cranelift/filetests/filetests/wasm/f32-compares.clif
@@ -1,8 +1,8 @@
 ; Test code generation for WebAssembly f32 comparison operators.
 test compile
 
+target aarch64
 target i686 haswell
-
 target x86_64 haswell
 
 function %f32_eq(f32, f32) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/f32-memory64.clif b/cranelift/filetests/filetests/wasm/f32-memory64.clif
index 33e3100537..9985898b79 100644
--- a/cranelift/filetests/filetests/wasm/f32-memory64.clif
+++ b/cranelift/filetests/filetests/wasm/f32-memory64.clif
@@ -3,6 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
+target aarch64
 target x86_64 haswell
 
 function %f32_load(i32, i64 vmctx) -> f32 {
diff --git a/cranelift/filetests/filetests/wasm/f64-arith.clif b/cranelift/filetests/filetests/wasm/f64-arith.clif
index cecd954f90..10699b1fd2 100644
--- a/cranelift/filetests/filetests/wasm/f64-arith.clif
+++ b/cranelift/filetests/filetests/wasm/f64-arith.clif
@@ -1,6 +1,7 @@
 ; Test basic code generation for f64 arithmetic WebAssembly instructions.
 test compile
 
+target aarch64
 target x86_64 haswell
 target x86_64 baseline
 
diff --git a/cranelift/filetests/filetests/wasm/f64-compares.clif b/cranelift/filetests/filetests/wasm/f64-compares.clif
index b75a7634bf..c372409251 100644
--- a/cranelift/filetests/filetests/wasm/f64-compares.clif
+++ b/cranelift/filetests/filetests/wasm/f64-compares.clif
@@ -1,8 +1,8 @@
 ; Test code generation for WebAssembly f64 comparison operators.
 test compile
 
+target aarch64
 target i686 haswell
-
 target x86_64 haswell
 
 function %f64_eq(f64, f64) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/f64-memory64.clif b/cranelift/filetests/filetests/wasm/f64-memory64.clif
index c0a58de4a1..f55a73fb87 100644
--- a/cranelift/filetests/filetests/wasm/f64-memory64.clif
+++ b/cranelift/filetests/filetests/wasm/f64-memory64.clif
@@ -3,6 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
+target aarch64
 target x86_64 haswell
 
 function %f64_load(i32, i64 vmctx) -> f64 {
diff --git a/cranelift/filetests/filetests/wasm/i32-arith.clif b/cranelift/filetests/filetests/wasm/i32-arith.clif
index cb9597741b..c82c24ae17 100644
--- a/cranelift/filetests/filetests/wasm/i32-arith.clif
+++ b/cranelift/filetests/filetests/wasm/i32-arith.clif
@@ -1,6 +1,7 @@
 ; Test basic code generation for i32 arithmetic WebAssembly instructions.
 test compile
 
+target aarch64
 target i686 haswell
 target i686 baseline
 target x86_64 haswell
diff --git a/cranelift/filetests/filetests/wasm/i32-compares.clif b/cranelift/filetests/filetests/wasm/i32-compares.clif
index f5be0a25c1..e6e64500c8 100644
--- a/cranelift/filetests/filetests/wasm/i32-compares.clif
+++ b/cranelift/filetests/filetests/wasm/i32-compares.clif
@@ -1,8 +1,8 @@
 ; Test code generation for WebAssembly i32 comparison operators.
 test compile
 
+target aarch64
 target i686 haswell
-
 target x86_64 haswell
 
 function %i32_eqz(i32) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/i32-memory64.clif b/cranelift/filetests/filetests/wasm/i32-memory64.clif
index b1418c5ed1..7fcf0316c2 100644
--- a/cranelift/filetests/filetests/wasm/i32-memory64.clif
+++ b/cranelift/filetests/filetests/wasm/i32-memory64.clif
@@ -3,6 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
+target aarch64
 target x86_64 haswell
 
 function %i32_load(i32, i64 vmctx) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/i64-arith.clif b/cranelift/filetests/filetests/wasm/i64-arith.clif
index b457f9942d..082f52a5ed 100644
--- a/cranelift/filetests/filetests/wasm/i64-arith.clif
+++ b/cranelift/filetests/filetests/wasm/i64-arith.clif
@@ -1,6 +1,7 @@
 ; Test basic code generation for i64 arithmetic WebAssembly instructions.
 test compile
 
+target aarch64
 target x86_64 haswell
 target x86_64 baseline
 
diff --git a/cranelift/filetests/filetests/wasm/i64-compares.clif b/cranelift/filetests/filetests/wasm/i64-compares.clif
index 2863efb6c3..c4df3e7e8c 100644
--- a/cranelift/filetests/filetests/wasm/i64-compares.clif
+++ b/cranelift/filetests/filetests/wasm/i64-compares.clif
@@ -1,6 +1,7 @@
 ; Test code generation for WebAssembly i64 comparison operators.
 test compile
 
+target aarch64
 target x86_64 haswell
 
 function %i64_eqz(i64) -> i32 {
diff --git a/cranelift/filetests/filetests/wasm/i64-memory64.clif b/cranelift/filetests/filetests/wasm/i64-memory64.clif
index f2b34fc8b0..7f76ccd86e 100644
--- a/cranelift/filetests/filetests/wasm/i64-memory64.clif
+++ b/cranelift/filetests/filetests/wasm/i64-memory64.clif
@@ -3,6 +3,7 @@ test compile
 
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
+target aarch64
 target x86_64 haswell
 
 function %i64_load(i32, i64 vmctx) -> i64 {
diff --git a/cranelift/filetests/filetests/wasm/multi-val-mixed.clif b/cranelift/filetests/filetests/wasm/multi-val-mixed.clif
index e7289332c7..98bc07a8da 100644
--- a/cranelift/filetests/filetests/wasm/multi-val-mixed.clif
+++ b/cranelift/filetests/filetests/wasm/multi-val-mixed.clif
@@ -1,4 +1,5 @@
 test compile
+target aarch64
 target x86_64 haswell
 
 ;; Returning many mixed values.
diff --git a/cranelift/filetests/filetests/wasm/multi-val-take-many-and-return-many.clif b/cranelift/filetests/filetests/wasm/multi-val-take-many-and-return-many.clif
index 17f2f306d4..4e36952f57 100644
--- a/cranelift/filetests/filetests/wasm/multi-val-take-many-and-return-many.clif
+++ b/cranelift/filetests/filetests/wasm/multi-val-take-many-and-return-many.clif
@@ -1,4 +1,5 @@
 test compile
+target aarch64
 target x86_64 haswell
 
 function %returner(i32, i64, f32, f64) -> i32, i64, f32, f64 {
diff --git a/cranelift/filetests/filetests/wasm/r32.clif b/cranelift/filetests/filetests/wasm/r32.clif
index 7e1622246a..49abed6907 100644
--- a/cranelift/filetests/filetests/wasm/r32.clif
+++ b/cranelift/filetests/filetests/wasm/r32.clif
@@ -4,6 +4,7 @@
 test compile
 set enable_safepoints=true
 
+target aarch64
 target i686 haswell
 
 function %select_ref(i32, r32, r32) -> r32 {
diff --git a/cranelift/filetests/filetests/wasm/r64.clif b/cranelift/filetests/filetests/wasm/r64.clif
index 9fab27fbb5..c0b09c1bdf 100644
--- a/cranelift/filetests/filetests/wasm/r64.clif
+++ b/cranelift/filetests/filetests/wasm/r64.clif
@@ -4,6 +4,7 @@
 test compile
 set enable_safepoints=true
 
+target aarch64
 target x86_64 haswell
 
 function %select_ref(i32, r64, r64) -> r64 {
diff --git a/cranelift/filetests/filetests/wasm/select.clif b/cranelift/filetests/filetests/wasm/select.clif
index b2508ef6e5..0b7a280259 100644
--- a/cranelift/filetests/filetests/wasm/select.clif
+++ b/cranelift/filetests/filetests/wasm/select.clif
@@ -1,8 +1,8 @@
 ; Test basic code generation for the select WebAssembly instruction.
 test compile
 
+target aarch64
 target i686 haswell
-
 target x86_64 haswell
 
 function %select_i32(i32, i32, i32) -> i32 {
diff --git a/cranelift/filetests/src/test_licm.rs b/cranelift/filetests/src/test_licm.rs
index a6be1d1fe7..ad23d281d1 100644
--- a/cranelift/filetests/src/test_licm.rs
+++ b/cranelift/filetests/src/test_licm.rs
@@ -26,6 +26,10 @@ impl SubTest for TestLICM {
         "licm"
     }
 
+    fn needs_isa(&self) -> bool {
+        true
+    }
+
     fn is_mutating(&self) -> bool {
         true
     }
diff --git a/cranelift/filetests/src/test_postopt.rs b/cranelift/filetests/src/test_postopt.rs
index 837257bbc0..ff7726d9c8 100644
--- a/cranelift/filetests/src/test_postopt.rs
+++ b/cranelift/filetests/src/test_postopt.rs
@@ -23,6 +23,10 @@ impl SubTest for TestPostopt {
         "postopt"
     }
 
+    fn needs_isa(&self) -> bool {
+        true
+    }
+
     fn is_mutating(&self) -> bool {
         true
     }
diff --git a/cranelift/filetests/src/test_simple_preopt.rs b/cranelift/filetests/src/test_simple_preopt.rs
index a47d64f5d1..2187afe0eb 100644
--- a/cranelift/filetests/src/test_simple_preopt.rs
+++ b/cranelift/filetests/src/test_simple_preopt.rs
@@ -23,6 +23,10 @@ impl SubTest for TestSimplePreopt {
         "simple_preopt"
     }
 
+    fn needs_isa(&self) -> bool {
+        true
+    }
+
     fn is_mutating(&self) -> bool {
         true
     }