Enable more CLIF tests on AArch64
The tests for the SIMD floating-point maximum and minimum operations require particular care because the handling of the NaN values is non-deterministic and may vary between platforms. There is no way to match several NaN values in a test, so the solution is to extract the non-deterministic test cases into a separate file that is subsequently replicated for every backend under test, with adjustments made to the expected results. Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
@@ -1,4 +1,5 @@
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test legalizer
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target aarch64
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target x86_64
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function %foo(i64, i64) -> i64 {
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@@ -1,4 +1,5 @@
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test legalizer
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target aarch64
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target i686
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function %foo() -> i64 {
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@@ -1,4 +1,5 @@
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test legalizer
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target aarch64
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target x86_64
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function u0:0(i128, i128, i64) -> i128 system_v {
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@@ -1,5 +1,6 @@
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test compile
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set opt_level=speed_and_size
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target aarch64
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target x86_64
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function %br_table_opt() {
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@@ -9,7 +10,7 @@ function %br_table_opt() {
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v0 = iconst.i32 1
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br_table v0, block2, jt0
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block1:
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block1:
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return
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block2:
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@@ -1,4 +1,5 @@
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test licm
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target aarch64
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target x86_64
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function %dont_hoist_jump_table_entry_during_licm() {
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@@ -1,5 +1,6 @@
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test licm
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target aarch64
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target x86_64
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;; Nontrapping readonly load from address that is not loop-dependent
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@@ -1,5 +1,6 @@
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test licm
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target aarch64
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target x86_64
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;; Nontrapping possibly-not-readonly load from address that is not
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@@ -1,5 +1,6 @@
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test licm
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target aarch64
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target x86_64
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;; Maybe-trapping readonly load from address that is not
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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function %icmp_to_brz_fold(i32) -> i32 {
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64 baseline
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; Cases where the denominator is created by an iconst
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target i686 baseline
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; -------- U32 --------
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target i686 baseline
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; -------- U32 --------
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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;; This file used to trigger assertions where we would keep trying to
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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;; Test that although v5 can be replaced with v1, we don't transplant `load.i32
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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function %wraparound(i64 vmctx) -> f32 system_v {
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target i686 baseline
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; -------- U32 --------
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target i686 baseline
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; -------- U32 --------
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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function u0:2(i64 , i64) {
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target i686
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;; 32-bits platforms.
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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;; 64-bits platforms.
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@@ -1,4 +1,5 @@
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test peepmatic
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target aarch64
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target x86_64
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;; The `isub` is a no-op, but we can't replace the whole `isub` instruction with
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@@ -1,4 +1,5 @@
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test postopt
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target aarch64
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target i686 legacy
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; Test that compare+branch sequences are folded effectively on x86.
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@@ -1,4 +1,5 @@
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test preopt
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target aarch64
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target x86_64
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function %brz_fold() -> i32 {
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@@ -1,4 +1,5 @@
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test preopt
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target aarch64
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target x86_64
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function %constant_fold(f64) -> f64 {
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@@ -1,4 +1,5 @@
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test preopt
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target aarch64
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target x86_64
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function %iadd_fold() -> i32 {
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@@ -33,4 +34,4 @@ block0:
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; nextln: v1 = iconst.i32 1
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; nextln: v2 = iconst.i32 41
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; nextln: return v2
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; nextln: }
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; nextln: }
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@@ -1,4 +1,5 @@
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test compile
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target aarch64
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target x86_64 legacy
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; This checks that code shrink is allowed while relaxing code, when code shrink
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@@ -1,4 +1,5 @@
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test run
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target aarch64
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target x86_64 machinst
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function %bint_b8_i128() -> i64, i64 {
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@@ -1,4 +1,5 @@
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test run
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target aarch64
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target x86_64 machinst
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target x86_64 legacy
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@@ -0,0 +1,23 @@
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; Test the non-deterministic aspects of the SIMD arithmetic operations.
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; If you change this file, you should most likely update
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; simd-arithmetic-nondeterministic*.clif as well.
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test run
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target aarch64
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function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmax v0, v1
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return v2
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}
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; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN:0x42 0.0]
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function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmin v0, v1
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return v2
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}
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; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN NaN]
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; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [NaN 0.0]
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; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN:0x42 0.0]
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@@ -0,0 +1,28 @@
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; Test the non-deterministic aspects of the SIMD arithmetic operations.
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; If you change this file, you should most likely update
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; simd-arithmetic-nondeterministic*.clif as well.
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test run
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set enable_simd
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target x86_64 machinst skylake
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function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmax v0, v1
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return v2
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}
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; note below how NaNs are quieted but (unlike fmin), retain their sign: this discrepancy is allowed by non-determinism
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; in the spec, see https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN 0.0]
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function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmin v0, v1
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return v2
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}
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; note below how NaNs are quieted and negative: this is due to non-determinism in the spec for NaNs, see
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; https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN -NaN]
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; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [-NaN 0.0]
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; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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@@ -1,5 +1,5 @@
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test run
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; target aarch64 TODO: Not yet implemented on aarch64
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target aarch64
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; target s390x TODO: Not yet implemented on s390x
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set enable_simd
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target x86_64 machinst skylake
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@@ -125,7 +125,7 @@ block0:
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; run
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function %sqrt_f64x2(f64x2) -> f64x2 {
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block0(v0: f64x2):
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block0(v0: f64x2):
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v1 = sqrt v0
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return v1
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}
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@@ -136,26 +136,22 @@ block0(v0: f64x2, v1: f64x2):
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v2 = fmax v0, v1
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return v2
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}
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; note below how NaNs are quieted but (unlike fmin), retain their sign: this discrepancy is allowed by non-determinism
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; in the spec, see https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; This operation exhibits non-deterministic behaviour for some input NaN values;
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; refer to the simd-arithmetic-nondeterministic*.clif files for the respective tests.
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; run: %fmax_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [+0x0.0 0x1.0]
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; run: %fmax_f64x2([-NaN NaN], [0x0.0 0x100.0]) == [-NaN NaN]
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; run: %fmax_f64x2([NaN 0.0], [0.0 0.0]) == [NaN 0.0]
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; run: %fmax_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN 0.0]
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function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmin v0, v1
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return v2
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}
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; note below how NaNs are quieted and negative: this is due to non-determinism in the spec for NaNs, see
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; https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; This operation exhibits non-deterministic behaviour for some input NaN values;
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; refer to the simd-arithmetic-nondeterministic*.clif files for the respective tests.
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; run: %fmin_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [-0x0.0 -0x1.0]
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; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN -NaN]
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; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [-NaN 0.0]
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; run: %fmin_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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function %fneg_f64x2(f64x2) -> f64x2 {
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block0(v0: f64x2):
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@@ -1,5 +1,6 @@
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test run
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set enable_simd
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target aarch64
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target x86_64 legacy skylake
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; TODO: once available, replace all lane extraction with `icmp + all_ones`
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@@ -1,5 +1,5 @@
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test run
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; target aarch64 TODO: Not yet implemented on aarch64
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target aarch64
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; target s390x TODO: Not yet implemented on s390x
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set enable_simd
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target x86_64 machinst
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@@ -1,5 +1,5 @@
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test run
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; target aarch64 TODO: Not yet implemented on aarch64
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target aarch64
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; target s390x TODO: Not yet implemented on s390x
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set enable_simd
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target x86_64 machinst
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@@ -1,6 +1,6 @@
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test run
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; target s390x TODO: Not yet implemented on s390x
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; target aarch64 TODO: Not yet implemented on aarch64
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target aarch64
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set enable_simd
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target x86_64 machinst
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set enable_simd
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@@ -1,5 +1,6 @@
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test simple-gvn
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target aarch64
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target x86_64
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function %eliminate_redundant_global_loads(i32, i64 vmctx) {
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@@ -1,4 +1,5 @@
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test simple_preopt
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target aarch64
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target x86_64
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;; Test replacement of bitselect with vselect for special masks
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@@ -1,4 +1,5 @@
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test simple_preopt
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target aarch64
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target x86_64
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function %icmp_to_brz_fold(i32) -> i32 {
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target x86_64 baseline
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|
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; Cases where the denominator is created by an iconst
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|
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target i686 baseline
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; -------- U32 --------
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|
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target i686 baseline
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; -------- U32 --------
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|
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target x86_64
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|
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;; Test that although v5 can be replaced with v1, we don't transplant `load.i32
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|
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@@ -1,4 +1,5 @@
|
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test simple_preopt
|
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target aarch64
|
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target x86_64
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|
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function %wraparound(i64 vmctx) -> f32 system_v {
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|
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@@ -1,4 +1,5 @@
|
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test simple_preopt
|
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target aarch64
|
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target i686 baseline
|
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|
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; -------- U32 --------
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|
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@@ -1,4 +1,5 @@
|
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test simple_preopt
|
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target aarch64
|
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target i686 baseline
|
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|
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; -------- U32 --------
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|
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@@ -1,4 +1,5 @@
|
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test simple_preopt
|
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target aarch64
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target x86_64
|
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|
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function u0:2(i64 , i64) {
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|
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@@ -1,4 +1,5 @@
|
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test simple_preopt
|
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target aarch64
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target x86_64
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;; Tests for sign-extending immediates.
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@@ -1,4 +1,5 @@
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test simple_preopt
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target aarch64
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target i686
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;; 32-bits platforms.
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target x86_64
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;; 64-bits platforms.
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|
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@@ -1,4 +1,5 @@
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test simple_preopt
|
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target aarch64
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target x86_64
|
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|
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;; The `isub` is a no-op, but we can't replace the whole `isub` instruction with
|
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|
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@@ -1,4 +1,5 @@
|
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test verifier
|
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target aarch64
|
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target i686
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|
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; Simple, correct use of CPU flags.
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|
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@@ -1,5 +1,6 @@
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test verifier
|
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set enable_simd=true
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target aarch64
|
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target x86_64
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function %scalar_to_vector() {
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|
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@@ -1,5 +1,6 @@
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test verifier
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set enable_simd
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target aarch64
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target x86_64
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|
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function %insertlane_i32x4() {
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|
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@@ -1,8 +1,8 @@
|
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; Test basic code generation for control flow WebAssembly instructions.
|
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test compile
|
||||
|
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target aarch64
|
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target i686 haswell
|
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|
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target x86_64 haswell
|
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|
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function %br_if(i32) -> i32 {
|
||||
|
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@@ -1,6 +1,7 @@
|
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; Test code generation for WebAssembly type conversion operators.
|
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test compile
|
||||
|
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target aarch64
|
||||
target x86_64 haswell
|
||||
|
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function %i32_wrap_i64(i64) -> i32 {
|
||||
|
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@@ -1,6 +1,7 @@
|
||||
; Test basic code generation for f32 arithmetic WebAssembly instructions.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
target i686 baseline
|
||||
target x86_64 haswell
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
; Test code generation for WebAssembly f32 comparison operators.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
|
||||
target x86_64 haswell
|
||||
|
||||
function %f32_eq(f32, f32) -> i32 {
|
||||
|
||||
@@ -3,6 +3,7 @@ test compile
|
||||
|
||||
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
|
||||
; explicitly mention the pointer width.
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %f32_load(i32, i64 vmctx) -> f32 {
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
; Test basic code generation for f64 arithmetic WebAssembly instructions.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
target x86_64 baseline
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
; Test code generation for WebAssembly f64 comparison operators.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
|
||||
target x86_64 haswell
|
||||
|
||||
function %f64_eq(f64, f64) -> i32 {
|
||||
|
||||
@@ -3,6 +3,7 @@ test compile
|
||||
|
||||
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
|
||||
; explicitly mention the pointer width.
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %f64_load(i32, i64 vmctx) -> f64 {
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
; Test basic code generation for i32 arithmetic WebAssembly instructions.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
target i686 baseline
|
||||
target x86_64 haswell
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
; Test code generation for WebAssembly i32 comparison operators.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
|
||||
target x86_64 haswell
|
||||
|
||||
function %i32_eqz(i32) -> i32 {
|
||||
|
||||
@@ -3,6 +3,7 @@ test compile
|
||||
|
||||
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
|
||||
; explicitly mention the pointer width.
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %i32_load(i32, i64 vmctx) -> i32 {
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
; Test basic code generation for i64 arithmetic WebAssembly instructions.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
target x86_64 baseline
|
||||
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
; Test code generation for WebAssembly i64 comparison operators.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %i64_eqz(i64) -> i32 {
|
||||
|
||||
@@ -3,6 +3,7 @@ test compile
|
||||
|
||||
; We only test on 64-bit since the heap_addr instructions and vmctx parameters
|
||||
; explicitly mention the pointer width.
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %i64_load(i32, i64 vmctx) -> i64 {
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
test compile
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
;; Returning many mixed values.
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
test compile
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %returner(i32, i64, f32, f64) -> i32, i64, f32, f64 {
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
test compile
|
||||
set enable_safepoints=true
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
|
||||
function %select_ref(i32, r32, r32) -> r32 {
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
test compile
|
||||
set enable_safepoints=true
|
||||
|
||||
target aarch64
|
||||
target x86_64 haswell
|
||||
|
||||
function %select_ref(i32, r64, r64) -> r64 {
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
; Test basic code generation for the select WebAssembly instruction.
|
||||
test compile
|
||||
|
||||
target aarch64
|
||||
target i686 haswell
|
||||
|
||||
target x86_64 haswell
|
||||
|
||||
function %select_i32(i32, i32, i32) -> i32 {
|
||||
|
||||
@@ -26,6 +26,10 @@ impl SubTest for TestLICM {
|
||||
"licm"
|
||||
}
|
||||
|
||||
fn needs_isa(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
fn is_mutating(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
@@ -23,6 +23,10 @@ impl SubTest for TestPostopt {
|
||||
"postopt"
|
||||
}
|
||||
|
||||
fn needs_isa(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
fn is_mutating(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
@@ -23,6 +23,10 @@ impl SubTest for TestSimplePreopt {
|
||||
"simple_preopt"
|
||||
}
|
||||
|
||||
fn needs_isa(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
fn is_mutating(&self) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user