Switch Cranelift over to regalloc2. (#3989)

This PR switches Cranelift over to the new register allocator, regalloc2.

See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801)
for a summary of the design changes. This switchover has implications for
core VCode/MachInst types and the lowering pass.

Overall, this change brings improvements to both compile time and speed of
generated code (runtime), as reported in #3942:

```
Benchmark       Compilation (wallclock)     Execution (wallclock)
blake3-scalar   25% faster                  28% faster
blake3-simd     no diff                     no diff
meshoptimizer   19% faster                  17% faster
pulldown-cmark  17% faster                  no diff
bz2             15% faster                  no diff
SpiderMonkey,   21% faster                  2% faster
  fib(30)
clang.wasm      42% faster                  N/A
```

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -10,16 +10,11 @@ block0(v0: i8, v1: i64, v2: i64):
   return v5
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   uxtb w0, w0
-;   Inst 1:   subs wzr, w0, #42
-;   Inst 2:   csel x0, x1, x2, eq
-;   Inst 3:   ret
-; }}
+; block0:
+;   uxtb w8, w0
+;   subs wzr, w8, #42
+;   csel x0, x1, x2, eq
+;   ret
 
 function %g(i8) -> b1 {
 block0(v0: i8):
@@ -29,16 +24,11 @@ block0(v0: i8):
   return v5
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   uxtb w0, w0
-;   Inst 1:   subs wzr, w0, #42
-;   Inst 2:   cset x0, eq
-;   Inst 3:   ret
-; }}
+; block0:
+;   uxtb w4, w0
+;   subs wzr, w4, #42
+;   cset x0, eq
+;   ret
 
 function %h(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):
@@ -46,16 +36,11 @@ block0(v0: i8, v1: i8, v2: i8):
   return v3
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   and x1, x1, x0
-;   Inst 1:   bic x0, x2, x0
-;   Inst 2:   orr x0, x0, x1
-;   Inst 3:   ret
-; }}
+; block0:
+;   and x8, x1, x0
+;   bic x0, x2, x0
+;   orr x0, x0, x8
+;   ret
 
 function %i(b1, i8, i8) -> i8 {
 block0(v0: b1, v1: i8, v2: i8):
@@ -63,16 +48,11 @@ block0(v0: b1, v1: i8, v2: i8):
   return v3
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   and w0, w0, #1
-;   Inst 1:   subs wzr, w0, wzr
-;   Inst 2:   csel x0, x1, x2, ne
-;   Inst 3:   ret
-; }}
+; block0:
+;   and w8, w0, #1
+;   subs wzr, w8, wzr
+;   csel x0, x1, x2, ne
+;   ret
 
 function %i(i32, i8, i8) -> i8 {
 block0(v0: i32, v1: i8, v2: i8):
@@ -82,15 +62,10 @@ block0(v0: i32, v1: i8, v2: i8):
   return v5
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 3)
-;   Inst 0:   subs wzr, w0, #42
-;   Inst 1:   csel x0, x1, x2, eq
-;   Inst 2:   ret
-; }}
+; block0:
+;   subs wzr, w0, #42
+;   csel x0, x1, x2, eq
+;   ret
 
 function %i128_select(b1, i128, i128) -> i128 {
 block0(v0: b1, v1: i128, v2: i128):
@@ -98,15 +73,10 @@ block0(v0: b1, v1: i128, v2: i128):
   return v3
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 5)
-;   Inst 0:   and w0, w0, #1
-;   Inst 1:   subs wzr, w0, wzr
-;   Inst 2:   csel x0, x2, x4, ne
-;   Inst 3:   csel x1, x3, x5, ne
-;   Inst 4:   ret
-; }}
+; block0:
+;   and w14, w0, #1
+;   subs wzr, w14, wzr
+;   csel x0, x2, x4, ne
+;   csel x1, x3, x5, ne
+;   ret