a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
83 lines
1.3 KiB
Plaintext
83 lines
1.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %f(i8, i64, i64) -> i64 {
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block0(v0: i8, v1: i64, v2: i64):
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v3 = iconst.i8 42
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v4 = ifcmp v0, v3
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v5 = selectif.i64 eq v4, v1, v2
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return v5
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}
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; block0:
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; uxtb w8, w0
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; subs wzr, w8, #42
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; csel x0, x1, x2, eq
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; ret
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function %g(i8) -> b1 {
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block0(v0: i8):
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v3 = iconst.i8 42
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v4 = ifcmp v0, v3
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v5 = trueif eq v4
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return v5
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}
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; block0:
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; uxtb w4, w0
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; subs wzr, w4, #42
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; cset x0, eq
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; ret
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function %h(i8, i8, i8) -> i8 {
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block0(v0: i8, v1: i8, v2: i8):
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v3 = bitselect.i8 v0, v1, v2
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return v3
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}
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; block0:
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; and x8, x1, x0
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; bic x0, x2, x0
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; orr x0, x0, x8
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; ret
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function %i(b1, i8, i8) -> i8 {
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block0(v0: b1, v1: i8, v2: i8):
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v3 = select.i8 v0, v1, v2
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return v3
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}
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; block0:
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; and w8, w0, #1
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; subs wzr, w8, wzr
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; csel x0, x1, x2, ne
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; ret
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function %i(i32, i8, i8) -> i8 {
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block0(v0: i32, v1: i8, v2: i8):
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v3 = iconst.i32 42
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v4 = icmp.i32 eq v0, v3
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v5 = select.i8 v4, v1, v2
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return v5
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}
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; block0:
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; subs wzr, w0, #42
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; csel x0, x1, x2, eq
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; ret
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function %i128_select(b1, i128, i128) -> i128 {
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block0(v0: b1, v1: i128, v2: i128):
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v3 = select.i128 v0, v1, v2
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return v3
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}
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; block0:
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; and w14, w0, #1
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; subs wzr, w14, wzr
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; csel x0, x2, x4, ne
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; csel x1, x3, x5, ne
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; ret
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