T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

s390x: update some regalloc metadata to remove use of reg_mod. (#4856)

Browse Source 
* s390x: update some regalloc metadata to remove use of `reg_mod`.

This is a step toward ultimately removing modify-operands, which along
with removal of pinned vregs, lets us move to a completely
constraint-based and fully-SSA regalloc input and get some nice
advantages eventually.

There are still a few uses of `mod` operands and pinned vregs remaining,
especially around the "regpair" abstraction. Those proved to be a bit
trickier to update though, so will have to be done separately.

* Review feedback: restore two-arg pretty-print form.

* Review feedback.
This commit is contained in:
Chris Fallin
2022-09-09 18:43:36 -05:00
committed by GitHub
parent 2986f6b0ff
commit 96bfd4e8c0
16 changed files with 653 additions and 420 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
cranelift/codegen/src/isa/s390x/abi.rs
View File

@@ -499,6 +499,7 @@ impl ABIMachineSpec for S390xMachineDeps {
insts.push(Inst::AluRUImm32 {
alu_op: ALUOp::AddLogical64,
rd: into_reg,
ri: into_reg.to_reg(),
imm,
});
}
@@ -546,12 +547,14 @@ impl ABIMachineSpec for S390xMachineDeps {
insts.push(Inst::AluRSImm16 {
alu_op: ALUOp::Add64,
rd: writable_stack_reg(),
ri: stack_reg(),
imm,
});
} else {
insts.push(Inst::AluRSImm32 {
alu_op: ALUOp::Add64,
rd: writable_stack_reg(),
ri: stack_reg(),
imm,
});
}

42
cranelift/codegen/src/isa/s390x/inst.isle
View File

@@ -27,6 +27,11 @@
(AluRR
(alu_op ALUOp)
(rd WritableReg)
;; Input side of `rd`. `rd` is constrained to reuse `ri`'s
;; allocation during regalloc. Hence, we have SSA form here (ri
;; is strictly a use, rd is strictly a def) and it becomes a
;; modified-reg form when encoded.
(ri Reg)
(rm Reg))
;; An ALU operation with a register in-/out operand and
@@ -34,6 +39,7 @@
(AluRX
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(mem MemArg))
;; An ALU operation with a register in-/out operand and a signed 16-bit
@@ -41,6 +47,7 @@
(AluRSImm16
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(imm i16))
;; An ALU operation with a register in-/out operand and a signed 32-bit
@@ -48,6 +55,7 @@
(AluRSImm32
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(imm i32))
;; An ALU operation with a register in-/out operand and an unsigned 32-bit
@@ -55,6 +63,7 @@
(AluRUImm32
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(imm u32))
;; An ALU operation with a register in-/out operand and a shifted 16-bit
@@ -62,6 +71,7 @@
(AluRUImm16Shifted
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(imm UImm16Shifted))
;; An ALU operation with a register in-/out operand and a shifted 32-bit
@@ -69,6 +79,7 @@
(AluRUImm32Shifted
(alu_op ALUOp)
(rd WritableReg)
(ri Reg)
(imm UImm32Shifted))
;; A multiply operation with two register sources and a register pair destination.
@@ -1999,50 +2010,50 @@
;; Helper for emitting `MInst.AluRR` instructions.
(decl alu_rr (Type ALUOp Reg Reg) Reg)
(rule (alu_rr ty op src1 src2)
(let ((dst WritableReg (copy_writable_reg ty src1))
(_ Unit (emit (MInst.AluRR op dst src2))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRR op dst src1 src2))))
dst))
;; Helper for emitting `MInst.AluRX` instructions.
(decl alu_rx (Type ALUOp Reg MemArg) Reg)
(rule (alu_rx ty op src mem)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRX op dst mem))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRX op dst src mem))))
dst))
;; Helper for emitting `MInst.AluRSImm16` instructions.
(decl alu_rsimm16 (Type ALUOp Reg i16) Reg)
(rule (alu_rsimm16 ty op src imm)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRSImm16 op dst imm))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRSImm16 op dst src imm))))
dst))
;; Helper for emitting `MInst.AluRSImm32` instructions.
(decl alu_rsimm32 (Type ALUOp Reg i32) Reg)
(rule (alu_rsimm32 ty op src imm)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRSImm32 op dst imm))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRSImm32 op dst src imm))))
dst))
;; Helper for emitting `MInst.AluRUImm32` instructions.
(decl alu_ruimm32 (Type ALUOp Reg u32) Reg)
(rule (alu_ruimm32 ty op src imm)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRUImm32 op dst imm))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRUImm32 op dst src imm))))
dst))
;; Helper for emitting `MInst.AluRUImm16Shifted` instructions.
(decl alu_ruimm16shifted (Type ALUOp Reg UImm16Shifted) Reg)
(rule (alu_ruimm16shifted ty op src imm)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRUImm16Shifted op dst imm))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRUImm16Shifted op dst src imm))))
dst))
;; Helper for emitting `MInst.AluRUImm32Shifted` instructions.
(decl alu_ruimm32shifted (Type ALUOp Reg UImm32Shifted) Reg)
(rule (alu_ruimm32shifted ty op src imm)
(let ((dst WritableReg (copy_writable_reg ty src))
(_ Unit (emit (MInst.AluRUImm32Shifted op dst imm))))
(let ((dst WritableReg (temp_writable_reg ty))
(_ Unit (emit (MInst.AluRUImm32Shifted op dst src imm))))
dst))
;; Helper for emitting `MInst.SMulWide` instructions.
@@ -2705,8 +2716,7 @@
;; Push a `MInst.AluRUImm32Shifted` instruction to a sequence.
(decl push_alu_uimm32shifted (VecMInstBuilder ALUOp WritableReg Reg UImm32Shifted) Reg)
(rule (push_alu_uimm32shifted ib op (real_reg dst) r imm)
(if (same_reg dst r))
(let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst imm))))
(let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst r imm))))
dst))
;; Push a `MInst.ShiftRR` instruction to a sequence.

67
cranelift/codegen/src/isa/s390x/inst/emit.rs
View File

@@ -1426,7 +1426,12 @@ impl MachInstEmit for Inst {
_ => unreachable!(),
};
if have_rr && rd.to_reg() == rn {
let inst = Inst::AluRR { alu_op, rd, rm };
let inst = Inst::AluRR {
alu_op,
rd,
ri: rn,
rm,
};
inst.emit(&[], sink, emit_info, state);
} else {
put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0));
@@ -1442,7 +1447,12 @@ impl MachInstEmit for Inst {
let rn = allocs.next(rn);
if rd.to_reg() == rn {
let inst = Inst::AluRSImm16 { alu_op, rd, imm };
let inst = Inst::AluRSImm16 {
alu_op,
rd,
ri: rn,
imm,
};
inst.emit(&[], sink, emit_info, state);
} else {
let opcode = match alu_op {
@@ -1453,8 +1463,10 @@ impl MachInstEmit for Inst {
put(sink, &enc_rie_d(opcode, rd.to_reg(), rn, imm as u16));
}
}
&Inst::AluRR { alu_op, rd, rm } => {
&Inst::AluRR { alu_op, rd, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);
let (opcode, is_rre) = match alu_op {
@@ -1490,9 +1502,12 @@ impl MachInstEmit for Inst {
&Inst::AluRX {
alu_op,
rd,
ri,
ref mem,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let mem = mem.with_allocs(&mut allocs);
let (opcode_rx, opcode_rxy) = match alu_op {
@@ -1530,8 +1545,15 @@ impl MachInstEmit for Inst {
rd, &mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state,
);
}
&Inst::AluRSImm16 { alu_op, rd, imm } => {
&Inst::AluRSImm16 {
alu_op,
rd,
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let opcode = match alu_op {
ALUOp::Add32 => 0xa7a, // AHI
@@ -1542,8 +1564,15 @@ impl MachInstEmit for Inst {
};
put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
}
&Inst::AluRSImm32 { alu_op, rd, imm } => {
&Inst::AluRSImm32 {
alu_op,
rd,
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let opcode = match alu_op {
ALUOp::Add32 => 0xc29, // AFI
@@ -1554,8 +1583,15 @@ impl MachInstEmit for Inst {
};
put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
}
&Inst::AluRUImm32 { alu_op, rd, imm } => {
&Inst::AluRUImm32 {
alu_op,
rd,
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let opcode = match alu_op {
ALUOp::AddLogical32 => 0xc2b, // ALFI
@@ -1566,8 +1602,15 @@ impl MachInstEmit for Inst {
};
put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
}
&Inst::AluRUImm16Shifted { alu_op, rd, imm } => {
&Inst::AluRUImm16Shifted {
alu_op,
rd,
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let opcode = match (alu_op, imm.shift) {
(ALUOp::And32, 0) => 0xa57, // NILL
@@ -1586,8 +1629,15 @@ impl MachInstEmit for Inst {
};
put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
}
&Inst::AluRUImm32Shifted { alu_op, rd, imm } => {
&Inst::AluRUImm32Shifted {
alu_op,
rd,
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
debug_assert_eq!(rd.to_reg(), ri);
let opcode = match (alu_op, imm.shift) {
(ALUOp::And32, 0) => 0xc0b, // NILF
@@ -3412,6 +3462,7 @@ impl MachInstEmit for Inst {
let inst = Inst::AluRX {
alu_op: ALUOp::Add64Ext32,
rd: rtmp,
ri: rtmp.to_reg(),
mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()),
};
inst.emit(&[], sink, emit_info, state);

104
cranelift/codegen/src/isa/s390x/inst/emit_tests.rs
View File

@@ -322,6 +322,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Add32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1A12",
@@ -331,6 +332,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Add64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9080045",
@@ -340,6 +342,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Add64Ext32,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9180045",
@@ -349,6 +352,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1E12",
@@ -358,6 +362,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B90A0045",
@@ -367,6 +372,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::AddLogical64Ext32,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B91A0045",
@@ -376,6 +382,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Sub32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1B12",
@@ -385,6 +392,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Sub64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9090045",
@@ -394,6 +402,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Sub64Ext32,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9190045",
@@ -403,6 +412,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1F12",
@@ -412,6 +422,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B90B0045",
@@ -421,6 +432,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::SubLogical64Ext32,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B91B0045",
@@ -430,6 +442,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Mul32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"B2520012",
@@ -439,6 +452,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Mul64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B90C0045",
@@ -448,6 +462,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Mul64Ext32,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B91C0045",
@@ -457,6 +472,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::And32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1412",
@@ -466,6 +482,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::And64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9800045",
@@ -475,6 +492,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Orr32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1612",
@@ -484,6 +502,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Orr64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9810045",
@@ -493,6 +512,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Xor32,
rd: writable_gpr(1),
ri: gpr(1),
rm: gpr(2),
},
"1712",
@@ -502,6 +522,7 @@ fn test_s390x_binemit() {
Inst::AluRR {
alu_op: ALUOp::Xor64,
rd: writable_gpr(4),
ri: gpr(4),
rm: gpr(5),
},
"B9820045",
@@ -512,6 +533,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -526,6 +548,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -540,6 +563,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -554,6 +578,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -568,6 +593,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -582,6 +608,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add64Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -596,6 +623,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Add64Ext32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -610,6 +638,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -624,6 +653,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -638,6 +668,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -652,6 +683,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::AddLogical64Ext32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -666,6 +698,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -680,6 +713,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -694,6 +728,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -708,6 +743,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -722,6 +758,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -736,6 +773,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub64Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -750,6 +788,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Sub64Ext32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -764,6 +803,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -778,6 +818,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -792,6 +833,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -806,6 +848,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::SubLogical64Ext32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -820,6 +863,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -834,6 +878,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -848,6 +893,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -862,6 +908,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul32Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -876,6 +923,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -890,6 +938,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul64Ext16,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -904,6 +953,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Mul64Ext32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -918,6 +968,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::And32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -932,6 +983,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::And32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -946,6 +998,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::And64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -960,6 +1013,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Orr32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -974,6 +1028,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Orr32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -988,6 +1043,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Orr64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -1002,6 +1058,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Xor32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -1016,6 +1073,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Xor32,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD20 {
base: gpr(2),
index: zero_reg(),
@@ -1030,6 +1088,7 @@ fn test_s390x_binemit() {
Inst::AluRX {
alu_op: ALUOp::Xor64,
rd: writable_gpr(1),
ri: gpr(1),
mem: MemArg::BXD12 {
base: gpr(2),
index: zero_reg(),
@@ -1045,6 +1104,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Add32,
rd: writable_gpr(7),
ri: gpr(7),
imm: -32768,
},
"A77A8000",
@@ -1054,6 +1114,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Add32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 32767,
},
"A77A7FFF",
@@ -1063,6 +1124,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Add64,
rd: writable_gpr(7),
ri: gpr(7),
imm: -32768,
},
"A77B8000",
@@ -1072,6 +1134,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Add64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 32767,
},
"A77B7FFF",
@@ -1081,6 +1144,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Mul32,
rd: writable_gpr(7),
ri: gpr(7),
imm: -32768,
},
"A77C8000",
@@ -1090,6 +1154,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Mul32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 32767,
},
"A77C7FFF",
@@ -1099,6 +1164,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Mul64,
rd: writable_gpr(7),
ri: gpr(7),
imm: -32768,
},
"A77D8000",
@@ -1108,6 +1174,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm16 {
alu_op: ALUOp::Mul64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 32767,
},
"A77D7FFF",
@@ -1118,6 +1185,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Add32,
rd: writable_gpr(7),
ri: gpr(7),
imm: -2147483648,
},
"C27980000000",
@@ -1127,6 +1195,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Add32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 2147483647,
},
"C2797FFFFFFF",
@@ -1136,6 +1205,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Mul32,
rd: writable_gpr(7),
ri: gpr(7),
imm: -2147483648,
},
"C27180000000",
@@ -1145,6 +1215,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Mul32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 2147483647,
},
"C2717FFFFFFF",
@@ -1154,6 +1225,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Add64,
rd: writable_gpr(7),
ri: gpr(7),
imm: -2147483648,
},
"C27880000000",
@@ -1163,6 +1235,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Add64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 2147483647,
},
"C2787FFFFFFF",
@@ -1172,6 +1245,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Mul64,
rd: writable_gpr(7),
ri: gpr(7),
imm: -2147483648,
},
"C27080000000",
@@ -1181,6 +1255,7 @@ fn test_s390x_binemit() {
Inst::AluRSImm32 {
alu_op: ALUOp::Mul64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 2147483647,
},
"C2707FFFFFFF",
@@ -1191,6 +1266,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 0,
},
"C27B00000000",
@@ -1200,6 +1276,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::AddLogical32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 4294967295,
},
"C27BFFFFFFFF",
@@ -1209,6 +1286,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 0,
},
"C27500000000",
@@ -1218,6 +1296,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::SubLogical32,
rd: writable_gpr(7),
ri: gpr(7),
imm: 4294967295,
},
"C275FFFFFFFF",
@@ -1227,6 +1306,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 0,
},
"C27A00000000",
@@ -1236,6 +1316,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::AddLogical64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 4294967295,
},
"C27AFFFFFFFF",
@@ -1245,6 +1326,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 0,
},
"C27400000000",
@@ -1254,6 +1336,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32 {
alu_op: ALUOp::SubLogical64,
rd: writable_gpr(7),
ri: gpr(7),
imm: 4294967295,
},
"C274FFFFFFFF",
@@ -1264,6 +1347,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(),
},
"A587FFFF",
@@ -1273,6 +1357,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(),
},
"A586FFFF",
@@ -1282,6 +1367,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
},
"A587FFFF",
@@ -1291,6 +1377,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
},
"A586FFFF",
@@ -1300,6 +1387,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
},
"A585FFFF",
@@ -1309,6 +1397,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
},
"A584FFFF",
@@ -1318,6 +1407,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(),
},
"A58BFFFF",
@@ -1327,6 +1417,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(),
},
"A58AFFFF",
@@ -1336,6 +1427,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
},
"A58BFFFF",
@@ -1345,6 +1437,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
},
"A58AFFFF",
@@ -1354,6 +1447,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
},
"A589FFFF",
@@ -1363,6 +1457,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm16Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
},
"A588FFFF",
@@ -1373,6 +1468,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::And32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
},
"C08BFFFFFFFF",
@@ -1382,6 +1478,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
},
"C08BFFFFFFFF",
@@ -1391,6 +1488,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::And64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
},
"C08AFFFFFFFF",
@@ -1400,6 +1498,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Orr32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
},
"C08DFFFFFFFF",
@@ -1409,6 +1508,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
},
"C08DFFFFFFFF",
@@ -1418,6 +1518,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Orr64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
},
"C08CFFFFFFFF",
@@ -1427,6 +1528,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Xor32,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
},
"C087FFFFFFFF",
@@ -1436,6 +1538,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Xor64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
},
"C087FFFFFFFF",
@@ -1445,6 +1548,7 @@ fn test_s390x_binemit() {
Inst::AluRUImm32Shifted {
alu_op: ALUOp::Xor64,
rd: writable_gpr(8),
ri: gpr(8),
imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
},
"C086FFFFFFFF",

103
cranelift/codegen/src/isa/s390x/inst/mod.rs
View File

@@ -476,28 +476,37 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
collector.reg_def(rd);
collector.reg_use(rn);
}
&Inst::AluRR { rd, rm, .. } => {
collector.reg_mod(rd);
&Inst::AluRR { rd, ri, rm, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_use(rm);
}
&Inst::AluRX { rd, ref mem, .. } => {
collector.reg_mod(rd);
&Inst::AluRX {
rd, ri, ref mem, ..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
memarg_operands(mem, collector);
}
&Inst::AluRSImm16 { rd, .. } => {
collector.reg_mod(rd);
&Inst::AluRSImm16 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
}
&Inst::AluRSImm32 { rd, .. } => {
collector.reg_mod(rd);
&Inst::AluRSImm32 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
}
&Inst::AluRUImm32 { rd, .. } => {
collector.reg_mod(rd);
&Inst::AluRUImm32 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
}
&Inst::AluRUImm16Shifted { rd, .. } => {
collector.reg_mod(rd);
&Inst::AluRUImm16Shifted { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
}
&Inst::AluRUImm32Shifted { rd, .. } => {
collector.reg_mod(rd);
&Inst::AluRUImm32Shifted { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
}
&Inst::SMulWide { rn, rm, .. } => {
collector.reg_use(rn);
@@ -1248,7 +1257,12 @@ impl Inst {
_ => unreachable!(),
};
if have_rr && rd.to_reg() == rn {
let inst = Inst::AluRR { alu_op, rd, rm };
let inst = Inst::AluRR {
alu_op,
rd,
ri: rd.to_reg(),
rm,
};
return inst.print_with_state(state, &mut empty_allocs);
}
let rd = pretty_print_reg(rd.to_reg(), &mut empty_allocs);
@@ -1266,7 +1280,12 @@ impl Inst {
let rn = allocs.next(rn);
if rd.to_reg() == rn {
let inst = Inst::AluRSImm16 { alu_op, rd, imm };
let inst = Inst::AluRSImm16 {
alu_op,
rd,
ri: rd.to_reg(),
imm,
};
return inst.print_with_state(state, &mut empty_allocs);
}
let op = match alu_op {
@@ -1278,7 +1297,7 @@ impl Inst {
let rn = pretty_print_reg(rn, &mut empty_allocs);
format!("{} {}, {}, {}", op, rd, rn, imm)
}
&Inst::AluRR { alu_op, rd, rm } => {
&Inst::AluRR { alu_op, rd, ri, rm } => {
let op = match alu_op {
ALUOp::Add32 => "ar",
ALUOp::Add64 => "agr",
@@ -1303,13 +1322,14 @@ impl Inst {
ALUOp::Xor64 => "xgr",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
let rm = pretty_print_reg(rm, allocs);
format!("{} {}, {}", op, rd, rm)
}
&Inst::AluRX {
alu_op,
rd,
ri,
ref mem,
} => {
let (opcode_rx, opcode_rxy) = match alu_op {
@@ -1343,7 +1363,7 @@ impl Inst {
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
let mem = mem.with_allocs(allocs);
let (mem_str, mem) = mem_finalize_for_show(
&mem,
@@ -1365,7 +1385,12 @@ impl Inst {
format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
}
&Inst::AluRSImm16 { alu_op, rd, imm } => {
&Inst::AluRSImm16 {
alu_op,
rd,
ri,
imm,
} => {
let op = match alu_op {
ALUOp::Add32 => "ahi",
ALUOp::Add64 => "aghi",
@@ -1373,10 +1398,15 @@ impl Inst {
ALUOp::Mul64 => "mghi",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("{} {}, {}", op, rd, imm)
}
&Inst::AluRSImm32 { alu_op, rd, imm } => {
&Inst::AluRSImm32 {
alu_op,
rd,
ri,
imm,
} => {
let op = match alu_op {
ALUOp::Add32 => "afi",
ALUOp::Add64 => "agfi",
@@ -1384,10 +1414,15 @@ impl Inst {
ALUOp::Mul64 => "msgfi",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("{} {}, {}", op, rd, imm)
}
&Inst::AluRUImm32 { alu_op, rd, imm } => {
&Inst::AluRUImm32 {
alu_op,
rd,
ri,
imm,
} => {
let op = match alu_op {
ALUOp::AddLogical32 => "alfi",
ALUOp::AddLogical64 => "algfi",
@@ -1395,10 +1430,15 @@ impl Inst {
ALUOp::SubLogical64 => "slgfi",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("{} {}, {}", op, rd, imm)
}
&Inst::AluRUImm16Shifted { alu_op, rd, imm } => {
&Inst::AluRUImm16Shifted {
alu_op,
rd,
ri,
imm,
} => {
let op = match (alu_op, imm.shift) {
(ALUOp::And32, 0) => "nill",
(ALUOp::And32, 1) => "nilh",
@@ -1414,10 +1454,15 @@ impl Inst {
(ALUOp::Orr64, 3) => "oihh",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("{} {}, {}", op, rd, imm.bits)
}
&Inst::AluRUImm32Shifted { alu_op, rd, imm } => {
&Inst::AluRUImm32Shifted {
alu_op,
rd,
ri,
imm,
} => {
let op = match (alu_op, imm.shift) {
(ALUOp::And32, 0) => "nilf",
(ALUOp::And64, 0) => "nilf",
@@ -1430,7 +1475,7 @@ impl Inst {
(ALUOp::Xor64, 1) => "xihf",
_ => unreachable!(),
};
let rd = pretty_print_reg(rd.to_reg(), allocs);
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("{} {}, {}", op, rd, imm.bits)
}
&Inst::SMulWide { rn, rm } => {

14
cranelift/codegen/src/isa/s390x/inst/regs.rs
View File

@@ -178,6 +178,20 @@ pub fn pretty_print_reg(reg: Reg, allocs: &mut AllocationConsumer<'_>) -> String
show_reg(reg)
}
pub fn pretty_print_reg_mod(
rd: Writable<Reg>,
ri: Reg,
allocs: &mut AllocationConsumer<'_>,
) -> String {
let output = allocs.next_writable(rd).to_reg();
let input = allocs.next(ri);
if output == input {
show_reg(output)
} else {
format!("{}<-{}", show_reg(output), show_reg(input))
}
}
pub fn pretty_print_fpr(reg: Reg, allocs: &mut AllocationConsumer<'_>) -> (String, Option<String>) {
let reg = allocs.next(reg);
(show_reg(reg), maybe_show_fpr(reg))