From 96bfd4e8c07aefa97fd2d91d2fe659560a85e395 Mon Sep 17 00:00:00 2001 From: Chris Fallin Date: Fri, 9 Sep 2022 18:43:36 -0500 Subject: [PATCH] s390x: update some regalloc metadata to remove use of `reg_mod`. (#4856) * s390x: update some regalloc metadata to remove use of `reg_mod`. This is a step toward ultimately removing modify-operands, which along with removal of pinned vregs, lets us move to a completely constraint-based and fully-SSA regalloc input and get some nice advantages eventually. There are still a few uses of `mod` operands and pinned vregs remaining, especially around the "regpair" abstraction. Those proved to be a bit trickier to update though, so will have to be done separately. * Review feedback: restore two-arg pretty-print form. * Review feedback. --- cranelift/codegen/src/isa/s390x/abi.rs | 3 + cranelift/codegen/src/isa/s390x/inst.isle | 42 ++-- cranelift/codegen/src/isa/s390x/inst/emit.rs | 67 +++++- .../codegen/src/isa/s390x/inst/emit_tests.rs | 104 +++++++++ cranelift/codegen/src/isa/s390x/inst/mod.rs | 103 ++++++--- cranelift/codegen/src/isa/s390x/inst/regs.rs | 14 ++ .../isa/s390x/atomic_cas-little.clif | 12 +- .../filetests/isa/s390x/atomic_cas.clif | 8 +- .../isa/s390x/atomic_rmw-arch13.clif | 33 +-- .../isa/s390x/atomic_rmw-little.clif | 199 +++++++++--------- .../filetests/isa/s390x/atomic_rmw.clif | 170 +++++++-------- .../filetests/filetests/isa/s390x/bitops.clif | 160 +++++++------- .../filetests/isa/s390x/bitwise.clif | 4 +- .../filetests/filetests/isa/s390x/call.clif | 2 - .../filetests/isa/s390x/conversions.clif | 30 +-- .../filetests/isa/s390x/shift-rotate.clif | 122 +++++------ 16 files changed, 653 insertions(+), 420 deletions(-) diff --git a/cranelift/codegen/src/isa/s390x/abi.rs b/cranelift/codegen/src/isa/s390x/abi.rs index 26f281586d..7a13a17f9d 100644 --- a/cranelift/codegen/src/isa/s390x/abi.rs +++ b/cranelift/codegen/src/isa/s390x/abi.rs @@ -499,6 +499,7 @@ impl ABIMachineSpec for S390xMachineDeps { insts.push(Inst::AluRUImm32 { alu_op: ALUOp::AddLogical64, rd: into_reg, + ri: into_reg.to_reg(), imm, }); } @@ -546,12 +547,14 @@ impl ABIMachineSpec for S390xMachineDeps { insts.push(Inst::AluRSImm16 { alu_op: ALUOp::Add64, rd: writable_stack_reg(), + ri: stack_reg(), imm, }); } else { insts.push(Inst::AluRSImm32 { alu_op: ALUOp::Add64, rd: writable_stack_reg(), + ri: stack_reg(), imm, }); } diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle index 56ade959f5..cf262d8281 100644 --- a/cranelift/codegen/src/isa/s390x/inst.isle +++ b/cranelift/codegen/src/isa/s390x/inst.isle @@ -27,6 +27,11 @@ (AluRR (alu_op ALUOp) (rd WritableReg) + ;; Input side of `rd`. `rd` is constrained to reuse `ri`'s + ;; allocation during regalloc. Hence, we have SSA form here (ri + ;; is strictly a use, rd is strictly a def) and it becomes a + ;; modified-reg form when encoded. + (ri Reg) (rm Reg)) ;; An ALU operation with a register in-/out operand and @@ -34,6 +39,7 @@ (AluRX (alu_op ALUOp) (rd WritableReg) + (ri Reg) (mem MemArg)) ;; An ALU operation with a register in-/out operand and a signed 16-bit @@ -41,6 +47,7 @@ (AluRSImm16 (alu_op ALUOp) (rd WritableReg) + (ri Reg) (imm i16)) ;; An ALU operation with a register in-/out operand and a signed 32-bit @@ -48,6 +55,7 @@ (AluRSImm32 (alu_op ALUOp) (rd WritableReg) + (ri Reg) (imm i32)) ;; An ALU operation with a register in-/out operand and an unsigned 32-bit @@ -55,6 +63,7 @@ (AluRUImm32 (alu_op ALUOp) (rd WritableReg) + (ri Reg) (imm u32)) ;; An ALU operation with a register in-/out operand and a shifted 16-bit @@ -62,6 +71,7 @@ (AluRUImm16Shifted (alu_op ALUOp) (rd WritableReg) + (ri Reg) (imm UImm16Shifted)) ;; An ALU operation with a register in-/out operand and a shifted 32-bit @@ -69,6 +79,7 @@ (AluRUImm32Shifted (alu_op ALUOp) (rd WritableReg) + (ri Reg) (imm UImm32Shifted)) ;; A multiply operation with two register sources and a register pair destination. @@ -1999,50 +2010,50 @@ ;; Helper for emitting `MInst.AluRR` instructions. (decl alu_rr (Type ALUOp Reg Reg) Reg) (rule (alu_rr ty op src1 src2) - (let ((dst WritableReg (copy_writable_reg ty src1)) - (_ Unit (emit (MInst.AluRR op dst src2)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRR op dst src1 src2)))) dst)) ;; Helper for emitting `MInst.AluRX` instructions. (decl alu_rx (Type ALUOp Reg MemArg) Reg) (rule (alu_rx ty op src mem) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRX op dst mem)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRX op dst src mem)))) dst)) ;; Helper for emitting `MInst.AluRSImm16` instructions. (decl alu_rsimm16 (Type ALUOp Reg i16) Reg) (rule (alu_rsimm16 ty op src imm) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRSImm16 op dst imm)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRSImm16 op dst src imm)))) dst)) ;; Helper for emitting `MInst.AluRSImm32` instructions. (decl alu_rsimm32 (Type ALUOp Reg i32) Reg) (rule (alu_rsimm32 ty op src imm) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRSImm32 op dst imm)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRSImm32 op dst src imm)))) dst)) ;; Helper for emitting `MInst.AluRUImm32` instructions. (decl alu_ruimm32 (Type ALUOp Reg u32) Reg) (rule (alu_ruimm32 ty op src imm) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRUImm32 op dst imm)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRUImm32 op dst src imm)))) dst)) ;; Helper for emitting `MInst.AluRUImm16Shifted` instructions. (decl alu_ruimm16shifted (Type ALUOp Reg UImm16Shifted) Reg) (rule (alu_ruimm16shifted ty op src imm) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRUImm16Shifted op dst imm)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRUImm16Shifted op dst src imm)))) dst)) ;; Helper for emitting `MInst.AluRUImm32Shifted` instructions. (decl alu_ruimm32shifted (Type ALUOp Reg UImm32Shifted) Reg) (rule (alu_ruimm32shifted ty op src imm) - (let ((dst WritableReg (copy_writable_reg ty src)) - (_ Unit (emit (MInst.AluRUImm32Shifted op dst imm)))) + (let ((dst WritableReg (temp_writable_reg ty)) + (_ Unit (emit (MInst.AluRUImm32Shifted op dst src imm)))) dst)) ;; Helper for emitting `MInst.SMulWide` instructions. @@ -2705,8 +2716,7 @@ ;; Push a `MInst.AluRUImm32Shifted` instruction to a sequence. (decl push_alu_uimm32shifted (VecMInstBuilder ALUOp WritableReg Reg UImm32Shifted) Reg) (rule (push_alu_uimm32shifted ib op (real_reg dst) r imm) - (if (same_reg dst r)) - (let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst imm)))) + (let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst r imm)))) dst)) ;; Push a `MInst.ShiftRR` instruction to a sequence. diff --git a/cranelift/codegen/src/isa/s390x/inst/emit.rs b/cranelift/codegen/src/isa/s390x/inst/emit.rs index d73a4e63a7..4bfe07e5b4 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit.rs @@ -1426,7 +1426,12 @@ impl MachInstEmit for Inst { _ => unreachable!(), }; if have_rr && rd.to_reg() == rn { - let inst = Inst::AluRR { alu_op, rd, rm }; + let inst = Inst::AluRR { + alu_op, + rd, + ri: rn, + rm, + }; inst.emit(&[], sink, emit_info, state); } else { put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0)); @@ -1442,7 +1447,12 @@ impl MachInstEmit for Inst { let rn = allocs.next(rn); if rd.to_reg() == rn { - let inst = Inst::AluRSImm16 { alu_op, rd, imm }; + let inst = Inst::AluRSImm16 { + alu_op, + rd, + ri: rn, + imm, + }; inst.emit(&[], sink, emit_info, state); } else { let opcode = match alu_op { @@ -1453,8 +1463,10 @@ impl MachInstEmit for Inst { put(sink, &enc_rie_d(opcode, rd.to_reg(), rn, imm as u16)); } } - &Inst::AluRR { alu_op, rd, rm } => { + &Inst::AluRR { alu_op, rd, ri, rm } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let rm = allocs.next(rm); let (opcode, is_rre) = match alu_op { @@ -1490,9 +1502,12 @@ impl MachInstEmit for Inst { &Inst::AluRX { alu_op, rd, + ri, ref mem, } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let mem = mem.with_allocs(&mut allocs); let (opcode_rx, opcode_rxy) = match alu_op { @@ -1530,8 +1545,15 @@ impl MachInstEmit for Inst { rd, &mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state, ); } - &Inst::AluRSImm16 { alu_op, rd, imm } => { + &Inst::AluRSImm16 { + alu_op, + rd, + ri, + imm, + } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let opcode = match alu_op { ALUOp::Add32 => 0xa7a, // AHI @@ -1542,8 +1564,15 @@ impl MachInstEmit for Inst { }; put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16)); } - &Inst::AluRSImm32 { alu_op, rd, imm } => { + &Inst::AluRSImm32 { + alu_op, + rd, + ri, + imm, + } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let opcode = match alu_op { ALUOp::Add32 => 0xc29, // AFI @@ -1554,8 +1583,15 @@ impl MachInstEmit for Inst { }; put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32)); } - &Inst::AluRUImm32 { alu_op, rd, imm } => { + &Inst::AluRUImm32 { + alu_op, + rd, + ri, + imm, + } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let opcode = match alu_op { ALUOp::AddLogical32 => 0xc2b, // ALFI @@ -1566,8 +1602,15 @@ impl MachInstEmit for Inst { }; put(sink, &enc_ril_a(opcode, rd.to_reg(), imm)); } - &Inst::AluRUImm16Shifted { alu_op, rd, imm } => { + &Inst::AluRUImm16Shifted { + alu_op, + rd, + ri, + imm, + } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let opcode = match (alu_op, imm.shift) { (ALUOp::And32, 0) => 0xa57, // NILL @@ -1586,8 +1629,15 @@ impl MachInstEmit for Inst { }; put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits)); } - &Inst::AluRUImm32Shifted { alu_op, rd, imm } => { + &Inst::AluRUImm32Shifted { + alu_op, + rd, + ri, + imm, + } => { let rd = allocs.next_writable(rd); + let ri = allocs.next(ri); + debug_assert_eq!(rd.to_reg(), ri); let opcode = match (alu_op, imm.shift) { (ALUOp::And32, 0) => 0xc0b, // NILF @@ -3412,6 +3462,7 @@ impl MachInstEmit for Inst { let inst = Inst::AluRX { alu_op: ALUOp::Add64Ext32, rd: rtmp, + ri: rtmp.to_reg(), mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()), }; inst.emit(&[], sink, emit_info, state); diff --git a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs index c1cbe87f88..3abdac0638 100644 --- a/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/s390x/inst/emit_tests.rs @@ -322,6 +322,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Add32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1A12", @@ -331,6 +332,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Add64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9080045", @@ -340,6 +342,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Add64Ext32, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9180045", @@ -349,6 +352,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::AddLogical32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1E12", @@ -358,6 +362,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::AddLogical64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B90A0045", @@ -367,6 +372,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::AddLogical64Ext32, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B91A0045", @@ -376,6 +382,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Sub32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1B12", @@ -385,6 +392,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Sub64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9090045", @@ -394,6 +402,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Sub64Ext32, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9190045", @@ -403,6 +412,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::SubLogical32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1F12", @@ -412,6 +422,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::SubLogical64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B90B0045", @@ -421,6 +432,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::SubLogical64Ext32, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B91B0045", @@ -430,6 +442,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Mul32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "B2520012", @@ -439,6 +452,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Mul64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B90C0045", @@ -448,6 +462,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Mul64Ext32, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B91C0045", @@ -457,6 +472,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::And32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1412", @@ -466,6 +482,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::And64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9800045", @@ -475,6 +492,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Orr32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1612", @@ -484,6 +502,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Orr64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9810045", @@ -493,6 +512,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Xor32, rd: writable_gpr(1), + ri: gpr(1), rm: gpr(2), }, "1712", @@ -502,6 +522,7 @@ fn test_s390x_binemit() { Inst::AluRR { alu_op: ALUOp::Xor64, rd: writable_gpr(4), + ri: gpr(4), rm: gpr(5), }, "B9820045", @@ -512,6 +533,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -526,6 +548,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -540,6 +563,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -554,6 +578,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -568,6 +593,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -582,6 +608,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add64Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -596,6 +623,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Add64Ext32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -610,6 +638,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::AddLogical32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -624,6 +653,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::AddLogical32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -638,6 +668,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::AddLogical64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -652,6 +683,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::AddLogical64Ext32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -666,6 +698,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -680,6 +713,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -694,6 +728,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -708,6 +743,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -722,6 +758,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -736,6 +773,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub64Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -750,6 +788,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Sub64Ext32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -764,6 +803,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::SubLogical32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -778,6 +818,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::SubLogical32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -792,6 +833,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::SubLogical64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -806,6 +848,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::SubLogical64Ext32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -820,6 +863,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -834,6 +878,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -848,6 +893,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -862,6 +908,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul32Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -876,6 +923,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -890,6 +938,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul64Ext16, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -904,6 +953,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Mul64Ext32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -918,6 +968,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::And32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -932,6 +983,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::And32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -946,6 +998,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::And64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -960,6 +1013,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Orr32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -974,6 +1028,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Orr32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -988,6 +1043,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Orr64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -1002,6 +1058,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Xor32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -1016,6 +1073,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Xor32, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD20 { base: gpr(2), index: zero_reg(), @@ -1030,6 +1088,7 @@ fn test_s390x_binemit() { Inst::AluRX { alu_op: ALUOp::Xor64, rd: writable_gpr(1), + ri: gpr(1), mem: MemArg::BXD12 { base: gpr(2), index: zero_reg(), @@ -1045,6 +1104,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Add32, rd: writable_gpr(7), + ri: gpr(7), imm: -32768, }, "A77A8000", @@ -1054,6 +1114,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Add32, rd: writable_gpr(7), + ri: gpr(7), imm: 32767, }, "A77A7FFF", @@ -1063,6 +1124,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Add64, rd: writable_gpr(7), + ri: gpr(7), imm: -32768, }, "A77B8000", @@ -1072,6 +1134,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Add64, rd: writable_gpr(7), + ri: gpr(7), imm: 32767, }, "A77B7FFF", @@ -1081,6 +1144,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Mul32, rd: writable_gpr(7), + ri: gpr(7), imm: -32768, }, "A77C8000", @@ -1090,6 +1154,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Mul32, rd: writable_gpr(7), + ri: gpr(7), imm: 32767, }, "A77C7FFF", @@ -1099,6 +1164,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Mul64, rd: writable_gpr(7), + ri: gpr(7), imm: -32768, }, "A77D8000", @@ -1108,6 +1174,7 @@ fn test_s390x_binemit() { Inst::AluRSImm16 { alu_op: ALUOp::Mul64, rd: writable_gpr(7), + ri: gpr(7), imm: 32767, }, "A77D7FFF", @@ -1118,6 +1185,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Add32, rd: writable_gpr(7), + ri: gpr(7), imm: -2147483648, }, "C27980000000", @@ -1127,6 +1195,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Add32, rd: writable_gpr(7), + ri: gpr(7), imm: 2147483647, }, "C2797FFFFFFF", @@ -1136,6 +1205,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Mul32, rd: writable_gpr(7), + ri: gpr(7), imm: -2147483648, }, "C27180000000", @@ -1145,6 +1215,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Mul32, rd: writable_gpr(7), + ri: gpr(7), imm: 2147483647, }, "C2717FFFFFFF", @@ -1154,6 +1225,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Add64, rd: writable_gpr(7), + ri: gpr(7), imm: -2147483648, }, "C27880000000", @@ -1163,6 +1235,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Add64, rd: writable_gpr(7), + ri: gpr(7), imm: 2147483647, }, "C2787FFFFFFF", @@ -1172,6 +1245,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Mul64, rd: writable_gpr(7), + ri: gpr(7), imm: -2147483648, }, "C27080000000", @@ -1181,6 +1255,7 @@ fn test_s390x_binemit() { Inst::AluRSImm32 { alu_op: ALUOp::Mul64, rd: writable_gpr(7), + ri: gpr(7), imm: 2147483647, }, "C2707FFFFFFF", @@ -1191,6 +1266,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::AddLogical32, rd: writable_gpr(7), + ri: gpr(7), imm: 0, }, "C27B00000000", @@ -1200,6 +1276,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::AddLogical32, rd: writable_gpr(7), + ri: gpr(7), imm: 4294967295, }, "C27BFFFFFFFF", @@ -1209,6 +1286,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::SubLogical32, rd: writable_gpr(7), + ri: gpr(7), imm: 0, }, "C27500000000", @@ -1218,6 +1296,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::SubLogical32, rd: writable_gpr(7), + ri: gpr(7), imm: 4294967295, }, "C275FFFFFFFF", @@ -1227,6 +1306,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::AddLogical64, rd: writable_gpr(7), + ri: gpr(7), imm: 0, }, "C27A00000000", @@ -1236,6 +1316,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::AddLogical64, rd: writable_gpr(7), + ri: gpr(7), imm: 4294967295, }, "C27AFFFFFFFF", @@ -1245,6 +1326,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::SubLogical64, rd: writable_gpr(7), + ri: gpr(7), imm: 0, }, "C27400000000", @@ -1254,6 +1336,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32 { alu_op: ALUOp::SubLogical64, rd: writable_gpr(7), + ri: gpr(7), imm: 4294967295, }, "C274FFFFFFFF", @@ -1264,6 +1347,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(), }, "A587FFFF", @@ -1273,6 +1357,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(), }, "A586FFFF", @@ -1282,6 +1367,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), }, "A587FFFF", @@ -1291,6 +1377,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), }, "A586FFFF", @@ -1300,6 +1387,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(), }, "A585FFFF", @@ -1309,6 +1397,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(), }, "A584FFFF", @@ -1318,6 +1407,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(), }, "A58BFFFF", @@ -1327,6 +1417,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(), }, "A58AFFFF", @@ -1336,6 +1427,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), }, "A58BFFFF", @@ -1345,6 +1437,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), }, "A58AFFFF", @@ -1354,6 +1447,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(), }, "A589FFFF", @@ -1363,6 +1457,7 @@ fn test_s390x_binemit() { Inst::AluRUImm16Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(), }, "A588FFFF", @@ -1373,6 +1468,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::And32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(), }, "C08BFFFFFFFF", @@ -1382,6 +1478,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(), }, "C08BFFFFFFFF", @@ -1391,6 +1488,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::And64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(), }, "C08AFFFFFFFF", @@ -1400,6 +1498,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Orr32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(), }, "C08DFFFFFFFF", @@ -1409,6 +1508,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(), }, "C08DFFFFFFFF", @@ -1418,6 +1518,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Orr64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(), }, "C08CFFFFFFFF", @@ -1427,6 +1528,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Xor32, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(), }, "C087FFFFFFFF", @@ -1436,6 +1538,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Xor64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(), }, "C087FFFFFFFF", @@ -1445,6 +1548,7 @@ fn test_s390x_binemit() { Inst::AluRUImm32Shifted { alu_op: ALUOp::Xor64, rd: writable_gpr(8), + ri: gpr(8), imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(), }, "C086FFFFFFFF", diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs index 283e6007e8..68cc20af91 100644 --- a/cranelift/codegen/src/isa/s390x/inst/mod.rs +++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs @@ -476,28 +476,37 @@ fn s390x_get_operands VReg>(inst: &Inst, collector: &mut OperandC collector.reg_def(rd); collector.reg_use(rn); } - &Inst::AluRR { rd, rm, .. } => { - collector.reg_mod(rd); + &Inst::AluRR { rd, ri, rm, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); collector.reg_use(rm); } - &Inst::AluRX { rd, ref mem, .. } => { - collector.reg_mod(rd); + &Inst::AluRX { + rd, ri, ref mem, .. + } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); memarg_operands(mem, collector); } - &Inst::AluRSImm16 { rd, .. } => { - collector.reg_mod(rd); + &Inst::AluRSImm16 { rd, ri, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); } - &Inst::AluRSImm32 { rd, .. } => { - collector.reg_mod(rd); + &Inst::AluRSImm32 { rd, ri, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); } - &Inst::AluRUImm32 { rd, .. } => { - collector.reg_mod(rd); + &Inst::AluRUImm32 { rd, ri, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); } - &Inst::AluRUImm16Shifted { rd, .. } => { - collector.reg_mod(rd); + &Inst::AluRUImm16Shifted { rd, ri, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); } - &Inst::AluRUImm32Shifted { rd, .. } => { - collector.reg_mod(rd); + &Inst::AluRUImm32Shifted { rd, ri, .. } => { + collector.reg_reuse_def(rd, 1); + collector.reg_use(ri); } &Inst::SMulWide { rn, rm, .. } => { collector.reg_use(rn); @@ -1248,7 +1257,12 @@ impl Inst { _ => unreachable!(), }; if have_rr && rd.to_reg() == rn { - let inst = Inst::AluRR { alu_op, rd, rm }; + let inst = Inst::AluRR { + alu_op, + rd, + ri: rd.to_reg(), + rm, + }; return inst.print_with_state(state, &mut empty_allocs); } let rd = pretty_print_reg(rd.to_reg(), &mut empty_allocs); @@ -1266,7 +1280,12 @@ impl Inst { let rn = allocs.next(rn); if rd.to_reg() == rn { - let inst = Inst::AluRSImm16 { alu_op, rd, imm }; + let inst = Inst::AluRSImm16 { + alu_op, + rd, + ri: rd.to_reg(), + imm, + }; return inst.print_with_state(state, &mut empty_allocs); } let op = match alu_op { @@ -1278,7 +1297,7 @@ impl Inst { let rn = pretty_print_reg(rn, &mut empty_allocs); format!("{} {}, {}, {}", op, rd, rn, imm) } - &Inst::AluRR { alu_op, rd, rm } => { + &Inst::AluRR { alu_op, rd, ri, rm } => { let op = match alu_op { ALUOp::Add32 => "ar", ALUOp::Add64 => "agr", @@ -1303,13 +1322,14 @@ impl Inst { ALUOp::Xor64 => "xgr", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); let rm = pretty_print_reg(rm, allocs); format!("{} {}, {}", op, rd, rm) } &Inst::AluRX { alu_op, rd, + ri, ref mem, } => { let (opcode_rx, opcode_rxy) = match alu_op { @@ -1343,7 +1363,7 @@ impl Inst { _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); let mem = mem.with_allocs(allocs); let (mem_str, mem) = mem_finalize_for_show( &mem, @@ -1365,7 +1385,12 @@ impl Inst { format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem) } - &Inst::AluRSImm16 { alu_op, rd, imm } => { + &Inst::AluRSImm16 { + alu_op, + rd, + ri, + imm, + } => { let op = match alu_op { ALUOp::Add32 => "ahi", ALUOp::Add64 => "aghi", @@ -1373,10 +1398,15 @@ impl Inst { ALUOp::Mul64 => "mghi", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); format!("{} {}, {}", op, rd, imm) } - &Inst::AluRSImm32 { alu_op, rd, imm } => { + &Inst::AluRSImm32 { + alu_op, + rd, + ri, + imm, + } => { let op = match alu_op { ALUOp::Add32 => "afi", ALUOp::Add64 => "agfi", @@ -1384,10 +1414,15 @@ impl Inst { ALUOp::Mul64 => "msgfi", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); format!("{} {}, {}", op, rd, imm) } - &Inst::AluRUImm32 { alu_op, rd, imm } => { + &Inst::AluRUImm32 { + alu_op, + rd, + ri, + imm, + } => { let op = match alu_op { ALUOp::AddLogical32 => "alfi", ALUOp::AddLogical64 => "algfi", @@ -1395,10 +1430,15 @@ impl Inst { ALUOp::SubLogical64 => "slgfi", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); format!("{} {}, {}", op, rd, imm) } - &Inst::AluRUImm16Shifted { alu_op, rd, imm } => { + &Inst::AluRUImm16Shifted { + alu_op, + rd, + ri, + imm, + } => { let op = match (alu_op, imm.shift) { (ALUOp::And32, 0) => "nill", (ALUOp::And32, 1) => "nilh", @@ -1414,10 +1454,15 @@ impl Inst { (ALUOp::Orr64, 3) => "oihh", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); format!("{} {}, {}", op, rd, imm.bits) } - &Inst::AluRUImm32Shifted { alu_op, rd, imm } => { + &Inst::AluRUImm32Shifted { + alu_op, + rd, + ri, + imm, + } => { let op = match (alu_op, imm.shift) { (ALUOp::And32, 0) => "nilf", (ALUOp::And64, 0) => "nilf", @@ -1430,7 +1475,7 @@ impl Inst { (ALUOp::Xor64, 1) => "xihf", _ => unreachable!(), }; - let rd = pretty_print_reg(rd.to_reg(), allocs); + let rd = pretty_print_reg_mod(rd, ri, allocs); format!("{} {}, {}", op, rd, imm.bits) } &Inst::SMulWide { rn, rm } => { diff --git a/cranelift/codegen/src/isa/s390x/inst/regs.rs b/cranelift/codegen/src/isa/s390x/inst/regs.rs index e272ac083b..16cd7a64d3 100644 --- a/cranelift/codegen/src/isa/s390x/inst/regs.rs +++ b/cranelift/codegen/src/isa/s390x/inst/regs.rs @@ -178,6 +178,20 @@ pub fn pretty_print_reg(reg: Reg, allocs: &mut AllocationConsumer<'_>) -> String show_reg(reg) } +pub fn pretty_print_reg_mod( + rd: Writable, + ri: Reg, + allocs: &mut AllocationConsumer<'_>, +) -> String { + let output = allocs.next_writable(rd).to_reg(); + let input = allocs.next(ri); + if output == input { + show_reg(output) + } else { + format!("{}<-{}", show_reg(output), show_reg(input)) + } +} + pub fn pretty_print_fpr(reg: Reg, allocs: &mut AllocationConsumer<'_>) -> (String, Option) { let reg = allocs.next(reg); (show_reg(reg), maybe_show_fpr(reg)) diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif index aa80954ccb..0e095ac4e4 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas-little.clif @@ -47,8 +47,8 @@ block0(v0: i64, v1: i16, v2: i16, v3: i64): ; lrvr %r3, %r3 ; l %r0, 0(%r5) ; 0: rll %r1, %r0, 16(%r4) ; rxsbg %r1, %r2, 176, 64, 48 ; jglh 1f ; risbgn %r1, %r3, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: -; rll %r3, %r0, 0(%r4) -; lrvr %r2, %r3 +; rll %r2, %r0, 0(%r4) +; lrvr %r2, %r2 ; lmg %r9, %r15, 72(%r15) ; br %r14 @@ -58,15 +58,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64): return v4 } -; stmg %r12, %r15, 96(%r15) +; stmg %r11, %r15, 88(%r15) ; block0: -; lgr %r12, %r4 +; lgr %r11, %r4 ; sllk %r4, %r5, 3 ; nill %r5, 65532 ; lcr %r2, %r4 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r12, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: ; rll %r2, %r0, 8(%r4) -; lmg %r12, %r15, 96(%r15) +; lmg %r11, %r15, 88(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif index f5720164ca..05e9650c65 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_cas.clif @@ -46,15 +46,15 @@ block0(v0: i64, v1: i8, v2: i8, v3: i64): return v4 } -; stmg %r12, %r15, 96(%r15) +; stmg %r11, %r15, 88(%r15) ; block0: -; lgr %r12, %r4 +; lgr %r11, %r4 ; sllk %r4, %r5, 3 ; nill %r5, 65532 ; lcr %r2, %r4 ; l %r0, 0(%r5) -; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r12, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: +; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r3, 160, 40, 24 ; jglh 1f ; risbgn %r1, %r11, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r5) ; jglh 0b ; 1: ; rll %r2, %r0, 8(%r4) -; lmg %r12, %r15, 96(%r15) +; lmg %r11, %r15, 88(%r15) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif index d8641224f1..498df64a16 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-arch13.clif @@ -32,11 +32,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r5, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -46,12 +47,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -87,14 +89,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; rnsbg %r1, %r5, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -104,11 +106,12 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif index 8fe0dbc7f3..b7ca9939a0 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw-little.clif @@ -38,14 +38,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; risbgn %r1, %r5, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 { @@ -55,12 +55,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; risbgn %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_add_i64(i64, i64, i64) -> i64 { @@ -94,14 +95,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; ar %r1, %r5 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_add_i8(i64, i64, i8) -> i8 { @@ -111,14 +112,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; ar %r1, %r5 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_sub_i64(i64, i64, i64) -> i64 { @@ -152,14 +152,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; sr %r1, %r5 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_sub_i8(i64, i64, i8) -> i8 { @@ -169,14 +169,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; sr %r1, %r5 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_and_i64(i64, i64, i64) -> i64 { @@ -210,14 +209,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; rnsbg %r1, %r5, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 { @@ -227,12 +226,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_or_i64(i64, i64, i64) -> i64 { @@ -266,14 +266,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; rosbg %r1, %r5, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 { @@ -283,12 +283,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rosbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_xor_i64(i64, i64, i64) -> i64 { @@ -322,14 +323,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; rxsbg %r1, %r5, 48, 64, 48 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 { @@ -339,12 +340,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -380,14 +382,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lrvr %r5, %r5 +; lrvr %r5, %r2 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; rnsbg %r1, %r5, 48, 64, 48 ; xilf %r1, 65535 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -397,12 +399,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 { @@ -436,14 +439,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_smin_i8(i64, i64, i8) -> i8 { @@ -453,14 +456,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 { @@ -494,14 +496,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_smax_i8(i64, i64, i8) -> i8 { @@ -511,14 +513,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 { @@ -552,14 +553,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_umin_i8(i64, i64, i8) -> i8 { @@ -569,14 +570,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 { @@ -610,14 +610,14 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r5, %r4 +; lgr %r2, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 16 +; sllk %r5, %r2, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 16(%r4) ; lrvr %r1, %r1 ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 48, 0 ; lrvr %r1, %r1 ; rll %r1, %r1, 16(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r4, %r0, 0(%r4) -; lrvr %r2, %r4 +; rll %r3, %r0, 0(%r4) +; lrvr %r2, %r3 ; br %r14 function %atomic_rmw_umax_i8(i64, i64, i8) -> i8 { @@ -627,13 +627,12 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif index 48677d0be1..f1bf6f23dc 100644 --- a/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif +++ b/cranelift/filetests/filetests/isa/s390x/atomic_rmw.clif @@ -36,11 +36,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; risbgn %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; risbgn %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_xchg_i8(i64, i64, i8) -> i8 { @@ -50,12 +51,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; risbgn %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; risbgn %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_add_i64(i64, i64) -> i64 { @@ -85,10 +87,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; ar %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -101,14 +103,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; ar %r1, %r5 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; ar %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_sub_i64(i64, i64) -> i64 { @@ -140,10 +141,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; sr %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -156,14 +157,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; sr %r1, %r5 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; sr %r1, %r5 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_and_i64(i64, i64) -> i64 { @@ -193,11 +193,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_and_i8(i64, i64, i8) -> i8 { @@ -207,12 +208,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_or_i64(i64, i64) -> i64 { @@ -242,11 +244,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rosbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rosbg %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_or_i8(i64, i64, i8) -> i8 { @@ -256,12 +259,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rosbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rosbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_xor_i64(i64, i64) -> i64 { @@ -291,11 +295,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rxsbg %r1, %r4, 32, 48, 16 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r5, 32, 48, 16 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_xor_i8(i64, i64, i8) -> i8 { @@ -305,12 +310,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rxsbg %r1, %r4, 32, 40, 24 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rxsbg %r1, %r2, 32, 40, 24 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_nand_i64(i64, i64, i64) -> i64 { @@ -344,11 +350,12 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r5, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 16(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r5, 32, 48, 16 ; xilf %r1, 4294901760 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 16(%r4) ; br %r14 function %atomic_rmw_nand_i8(i64, i64, i8) -> i8 { @@ -358,12 +365,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; sllk %r5, %r3, 3 +; lgr %r2, %r4 +; sllk %r4, %r3, 3 ; nill %r3, 65532 -; lcr %r2, %r5 +; lcr %r5, %r4 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r5) ; rnsbg %r1, %r4, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r5) +; 0: rll %r1, %r0, 0(%r4) ; rnsbg %r1, %r2, 32, 40, 24 ; xilf %r1, 4278190080 ; rll %r1, %r1, 0(%r5) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r4) ; br %r14 function %atomic_rmw_smin_i64(i64, i64, i64) -> i64 { @@ -397,10 +405,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 48, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -413,14 +421,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_smax_i64(i64, i64, i64) -> i64 { @@ -454,10 +461,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 48, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -470,14 +477,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; cr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umin_i64(i64, i64, i64) -> i64 { @@ -511,10 +517,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 48, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -527,14 +533,13 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r5, %r1 ; jgnl 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 function %atomic_rmw_umax_i64(i64, i64, i64) -> i64 { @@ -568,10 +573,10 @@ block0(v0: i64, v1: i64, v2: i16): } ; block0: -; lgr %r2, %r4 +; lgr %r5, %r4 ; sllk %r4, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r2, 16 +; sllk %r5, %r5, 16 ; l %r0, 0(%r3) ; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 48, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: ; rll %r2, %r0, 16(%r4) @@ -584,13 +589,12 @@ block0(v0: i64, v1: i64, v2: i8): } ; block0: -; lgr %r5, %r4 -; sllk %r4, %r3, 3 +; sllk %r2, %r3, 3 ; nill %r3, 65532 -; sllk %r5, %r5, 24 -; lcr %r2, %r4 +; sllk %r5, %r4, 24 +; lcr %r4, %r2 ; l %r0, 0(%r3) -; 0: rll %r1, %r0, 0(%r4) ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r2) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: -; rll %r2, %r0, 8(%r4) +; 0: rll %r1, %r0, 0(%r2) ; clr %r5, %r1 ; jgnh 1f ; risbgn %r1, %r5, 32, 40, 0 ; rll %r1, %r1, 0(%r4) ; cs %r0, %r1, 0(%r3) ; jglh 0b ; 1: +; rll %r2, %r0, 8(%r2) ; br %r14 diff --git a/cranelift/filetests/filetests/isa/s390x/bitops.clif b/cranelift/filetests/filetests/isa/s390x/bitops.clif index 2213deb118..6ea451147d 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitops.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitops.clif @@ -36,34 +36,36 @@ block0(v0: i64): } ; block0: -; llihf %r5, 2863311530 -; iilf %r5, 2863311530 -; sllg %r4, %r2, 1 -; srlg %r2, %r2, 1 -; ngr %r4, %r5 -; xilf %r5, 4294967295 -; xihf %r5, 4294967295 -; ngrk %r5, %r2, %r5 -; ogrk %r2, %r4, %r5 -; llihf %r4, 3435973836 -; iilf %r4, 3435973836 -; sllg %r3, %r2, 2 -; srlg %r5, %r2, 2 -; ngr %r3, %r4 -; xilf %r4, 4294967295 -; xihf %r4, 4294967295 -; ngrk %r4, %r5, %r4 -; ogrk %r5, %r3, %r4 -; llihf %r3, 4042322160 -; iilf %r3, 4042322160 -; sllg %r2, %r5, 4 -; srlg %r4, %r5, 4 -; ngr %r2, %r3 +; lgr %r3, %r2 +; llihf %r2, 2863311530 +; iilf %r2, 2863311530 +; lgr %r5, %r3 +; sllg %r4, %r5, 1 +; srlg %r3, %r5, 1 +; ngr %r4, %r2 +; xilf %r2, 4294967295 +; xihf %r2, 4294967295 +; ngrk %r2, %r3, %r2 +; ogr %r4, %r2 +; llihf %r3, 3435973836 +; iilf %r3, 3435973836 +; sllg %r5, %r4, 2 +; srlg %r4, %r4, 2 +; ngr %r5, %r3 ; xilf %r3, 4294967295 ; xihf %r3, 4294967295 ; ngrk %r3, %r4, %r3 -; ogrk %r4, %r2, %r3 -; lrvgr %r2, %r4 +; ogr %r5, %r3 +; llihf %r4, 4042322160 +; iilf %r4, 4042322160 +; sllg %r2, %r5, 4 +; srlg %r5, %r5, 4 +; ngr %r2, %r4 +; xilf %r4, 4294967295 +; xihf %r4, 4294967295 +; ngrk %r4, %r5, %r4 +; ogr %r2, %r4 +; lrvgr %r2, %r2 ; br %r14 function %bitrev_i32(i32) -> i32 { @@ -79,22 +81,22 @@ block0(v0: i32): ; nr %r3, %r5 ; xilf %r5, 4294967295 ; nrk %r4, %r2, %r5 -; ork %r2, %r3, %r4 -; iilf %r4, 3435973836 -; sllk %r3, %r2, 2 -; srlk %r5, %r2, 2 -; nrk %r2, %r3, %r4 -; xilf %r4, 4294967295 -; nrk %r3, %r5, %r4 -; ork %r5, %r2, %r3 -; iilf %r3, 4042322160 -; sllk %r2, %r5, 4 -; srlk %r4, %r5, 4 +; ork %r5, %r3, %r4 +; iilf %r3, 3435973836 +; sllk %r2, %r5, 2 +; srlk %r4, %r5, 2 ; nrk %r5, %r2, %r3 ; xilf %r3, 4294967295 ; nrk %r2, %r4, %r3 -; ork %r4, %r5, %r2 -; lrvr %r2, %r4 +; ork %r3, %r5, %r2 +; iilf %r5, 4042322160 +; sllk %r4, %r3, 4 +; srlk %r2, %r3, 4 +; nrk %r3, %r4, %r5 +; xilf %r5, 4294967295 +; nrk %r4, %r2, %r5 +; ork %r5, %r3, %r4 +; lrvr %r2, %r5 ; br %r14 function %bitrev_i16(i16) -> i16 { @@ -110,23 +112,23 @@ block0(v0: i16): ; nr %r3, %r5 ; xilf %r5, 4294967295 ; nrk %r4, %r2, %r5 -; ork %r2, %r3, %r4 -; lhi %r4, -13108 -; sllk %r3, %r2, 2 -; srlk %r5, %r2, 2 -; nrk %r2, %r3, %r4 -; xilf %r4, 4294967295 -; nrk %r3, %r5, %r4 -; ork %r5, %r2, %r3 -; lhi %r3, -3856 -; sllk %r2, %r5, 4 -; srlk %r4, %r5, 4 +; ork %r5, %r3, %r4 +; lhi %r3, -13108 +; sllk %r2, %r5, 2 +; srlk %r4, %r5, 2 ; nrk %r5, %r2, %r3 ; xilf %r3, 4294967295 ; nrk %r2, %r4, %r3 -; ork %r4, %r5, %r2 -; lrvr %r2, %r4 -; srlk %r2, %r2, 16 +; ork %r3, %r5, %r2 +; lhi %r5, -3856 +; sllk %r4, %r3, 4 +; srlk %r2, %r3, 4 +; nrk %r3, %r4, %r5 +; xilf %r5, 4294967295 +; nrk %r4, %r2, %r5 +; ork %r5, %r3, %r4 +; lrvr %r3, %r5 +; srlk %r2, %r3, 16 ; br %r14 function %bitrev_i8(i8) -> i8 { @@ -142,21 +144,21 @@ block0(v0: i8): ; nr %r3, %r5 ; xilf %r5, 4294967295 ; nrk %r4, %r2, %r5 -; ork %r2, %r3, %r4 -; lhi %r4, -13108 -; sllk %r3, %r2, 2 -; srlk %r5, %r2, 2 -; nrk %r2, %r3, %r4 -; xilf %r4, 4294967295 -; nrk %r3, %r5, %r4 -; ork %r5, %r2, %r3 -; lhi %r3, -3856 -; sllk %r2, %r5, 4 -; srlk %r4, %r5, 4 +; ork %r5, %r3, %r4 +; lhi %r3, -13108 +; sllk %r2, %r5, 2 +; srlk %r4, %r5, 2 ; nrk %r5, %r2, %r3 ; xilf %r3, 4294967295 ; nrk %r2, %r4, %r3 -; ork %r2, %r5, %r2 +; ork %r3, %r5, %r2 +; lhi %r5, -3856 +; sllk %r4, %r3, 4 +; srlk %r2, %r3, 4 +; nrk %r3, %r4, %r5 +; xilf %r5, 4294967295 +; nrk %r4, %r2, %r5 +; ork %r2, %r3, %r4 ; br %r14 function %clz_i128(i128) -> i128 { @@ -346,11 +348,11 @@ block0(v0: i32): ; block0: ; oihl %r2, 1 -; lcgr %r4, %r2 -; ngr %r2, %r4 -; flogr %r0, %r2 -; lhi %r5, 63 -; srk %r2, %r5, %r0 +; lcgr %r3, %r2 +; ngrk %r5, %r2, %r3 +; flogr %r0, %r5 +; lhi %r4, 63 +; srk %r2, %r4, %r0 ; br %r14 function %ctz_i16(i16) -> i16 { @@ -361,11 +363,11 @@ block0(v0: i16): ; block0: ; oilh %r2, 1 -; lcgr %r4, %r2 -; ngr %r2, %r4 -; flogr %r0, %r2 -; lhi %r5, 63 -; srk %r2, %r5, %r0 +; lcgr %r3, %r2 +; ngrk %r5, %r2, %r3 +; flogr %r0, %r5 +; lhi %r4, 63 +; srk %r2, %r4, %r0 ; br %r14 function %ctz_i8(i8) -> i8 { @@ -376,11 +378,11 @@ block0(v0: i8): ; block0: ; oill %r2, 256 -; lcgr %r4, %r2 -; ngr %r2, %r4 -; flogr %r0, %r2 -; lhi %r5, 63 -; srk %r2, %r5, %r0 +; lcgr %r3, %r2 +; ngrk %r5, %r2, %r3 +; flogr %r0, %r5 +; lhi %r4, 63 +; srk %r2, %r4, %r0 ; br %r14 function %popcnt_i128(i128) -> i128 { diff --git a/cranelift/filetests/filetests/isa/s390x/bitwise.clif b/cranelift/filetests/filetests/isa/s390x/bitwise.clif index d7a8ce5e0a..affc376914 100644 --- a/cranelift/filetests/filetests/isa/s390x/bitwise.clif +++ b/cranelift/filetests/filetests/isa/s390x/bitwise.clif @@ -585,8 +585,8 @@ block0(v0: i64, v1: i64, v2: i64): ; ngr %r3, %r2 ; xilf %r2, 4294967295 ; xihf %r2, 4294967295 -; ngr %r4, %r2 -; ogrk %r2, %r4, %r3 +; ngrk %r5, %r4, %r2 +; ogrk %r2, %r5, %r3 ; br %r14 function %bitselect_i32(i32, i32, i32) -> i32 { diff --git a/cranelift/filetests/filetests/isa/s390x/call.clif b/cranelift/filetests/filetests/isa/s390x/call.clif index 0e9cfdcb0b..dbfe73b088 100644 --- a/cranelift/filetests/filetests/isa/s390x/call.clif +++ b/cranelift/filetests/filetests/isa/s390x/call.clif @@ -125,8 +125,6 @@ block0(v0: i64, v1: i64): ; lmg %r14, %r15, 272(%r15) ; br %r14 - - function %incoming_args(i64, i32, i32 uext, i32 sext, i16, i16 uext, i16 sext, i8, i8 uext, i8 sext) -> i64 { block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8: i8, v9: i8): v10 = uextend.i64 v1 diff --git a/cranelift/filetests/filetests/isa/s390x/conversions.clif b/cranelift/filetests/filetests/isa/s390x/conversions.clif index 0faff0b133..b9b36fdbf6 100644 --- a/cranelift/filetests/filetests/isa/s390x/conversions.clif +++ b/cranelift/filetests/filetests/isa/s390x/conversions.clif @@ -1031,9 +1031,9 @@ block0(v0: b64): ; block0: ; nill %r3, 1 -; vgbm %v7, 0 -; vlvgb %v7, %r3, 15 -; vst %v7, 0(%r2) +; vgbm %v6, 0 +; vlvgb %v6, %r3, 15 +; vst %v6, 0(%r2) ; br %r14 function %bint_b64_i64(b64) -> i64 { @@ -1085,9 +1085,9 @@ block0(v0: b32): ; block0: ; nill %r3, 1 -; vgbm %v7, 0 -; vlvgb %v7, %r3, 15 -; vst %v7, 0(%r2) +; vgbm %v6, 0 +; vlvgb %v6, %r3, 15 +; vst %v6, 0(%r2) ; br %r14 function %bint_b32_i64(b32) -> i64 { @@ -1139,9 +1139,9 @@ block0(v0: b16): ; block0: ; nill %r3, 1 -; vgbm %v7, 0 -; vlvgb %v7, %r3, 15 -; vst %v7, 0(%r2) +; vgbm %v6, 0 +; vlvgb %v6, %r3, 15 +; vst %v6, 0(%r2) ; br %r14 function %bint_b16_i64(b16) -> i64 { @@ -1193,9 +1193,9 @@ block0(v0: b8): ; block0: ; nill %r3, 1 -; vgbm %v7, 0 -; vlvgb %v7, %r3, 15 -; vst %v7, 0(%r2) +; vgbm %v6, 0 +; vlvgb %v6, %r3, 15 +; vst %v6, 0(%r2) ; br %r14 function %bint_b8_i64(b8) -> i64 { @@ -1247,9 +1247,9 @@ block0(v0: b1): ; block0: ; nill %r3, 1 -; vgbm %v7, 0 -; vlvgb %v7, %r3, 15 -; vst %v7, 0(%r2) +; vgbm %v6, 0 +; vlvgb %v6, %r3, 15 +; vst %v6, 0(%r2) ; br %r14 function %bint_b1_i64(b1) -> i64 { diff --git a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif index 2d704655b3..4163806b99 100644 --- a/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif +++ b/cranelift/filetests/filetests/isa/s390x/shift-rotate.clif @@ -137,13 +137,13 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llhr %r3, %r2 -; vlgvg %r5, %v1, 1 -; lcr %r4, %r5 -; nill %r5, 15 +; vlgvg %r4, %v1, 1 +; lcr %r5, %r4 ; nill %r4, 15 -; sllk %r4, %r3, 0(%r4) -; srlk %r5, %r3, 0(%r5) -; ork %r2, %r4, %r5 +; nill %r5, 15 +; sllk %r5, %r3, 0(%r5) +; srlk %r3, %r3, 0(%r4) +; ork %r2, %r5, %r3 ; br %r14 function %rotr_i16_reg(i16, i16) -> i16 { @@ -158,8 +158,8 @@ block0(v0: i16, v1: i16): ; nill %r3, 15 ; nill %r4, 15 ; sllk %r4, %r2, 0(%r4) -; srlk %r2, %r2, 0(%r3) -; ork %r2, %r4, %r2 +; srlk %r5, %r2, 0(%r3) +; ork %r2, %r4, %r5 ; br %r14 function %rotr_i16_imm(i16) -> i16 { @@ -185,13 +185,13 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llcr %r3, %r2 -; vlgvg %r5, %v1, 1 -; lcr %r4, %r5 -; nill %r5, 7 +; vlgvg %r4, %v1, 1 +; lcr %r5, %r4 ; nill %r4, 7 -; sllk %r4, %r3, 0(%r4) -; srlk %r5, %r3, 0(%r5) -; ork %r2, %r4, %r5 +; nill %r5, 7 +; sllk %r5, %r3, 0(%r5) +; srlk %r3, %r3, 0(%r4) +; ork %r2, %r5, %r3 ; br %r14 function %rotr_i8_reg(i8, i8) -> i8 { @@ -206,8 +206,8 @@ block0(v0: i8, v1: i8): ; nill %r3, 7 ; nill %r4, 7 ; sllk %r4, %r2, 0(%r4) -; srlk %r2, %r2, 0(%r3) -; ork %r2, %r4, %r2 +; srlk %r5, %r2, 0(%r3) +; ork %r2, %r4, %r5 ; br %r14 function %rotr_i8_imm(i8) -> i8 { @@ -356,13 +356,13 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llhr %r3, %r2 -; vlgvg %r5, %v1, 1 -; lcr %r4, %r5 -; nill %r5, 15 +; vlgvg %r4, %v1, 1 +; lcr %r5, %r4 ; nill %r4, 15 -; sllk %r5, %r3, 0(%r5) -; srlk %r2, %r3, 0(%r4) -; ork %r2, %r5, %r2 +; nill %r5, 15 +; sllk %r2, %r3, 0(%r4) +; srlk %r3, %r3, 0(%r5) +; or %r2, %r3 ; br %r14 function %rotl_i16_reg(i16, i16) -> i16 { @@ -376,9 +376,9 @@ block0(v0: i16, v1: i16): ; lcr %r4, %r3 ; nill %r3, 15 ; nill %r4, 15 -; sllk %r5, %r2, 0(%r3) -; srlk %r2, %r2, 0(%r4) -; ork %r2, %r5, %r2 +; sllk %r3, %r2, 0(%r3) +; srlk %r4, %r2, 0(%r4) +; ork %r2, %r3, %r4 ; br %r14 function %rotl_i16_imm(i16) -> i16 { @@ -404,13 +404,13 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llcr %r3, %r2 -; vlgvg %r5, %v1, 1 -; lcr %r4, %r5 -; nill %r5, 7 +; vlgvg %r4, %v1, 1 +; lcr %r5, %r4 ; nill %r4, 7 -; sllk %r5, %r3, 0(%r5) -; srlk %r2, %r3, 0(%r4) -; ork %r2, %r5, %r2 +; nill %r5, 7 +; sllk %r2, %r3, 0(%r4) +; srlk %r3, %r3, 0(%r5) +; or %r2, %r3 ; br %r14 function %rotl_i8_reg(i8, i8) -> i8 { @@ -424,9 +424,9 @@ block0(v0: i8, v1: i8): ; lcr %r4, %r3 ; nill %r3, 7 ; nill %r4, 7 -; sllk %r5, %r2, 0(%r3) -; srlk %r2, %r2, 0(%r4) -; ork %r2, %r5, %r2 +; sllk %r3, %r2, 0(%r3) +; srlk %r4, %r2, 0(%r4) +; ork %r2, %r3, %r4 ; br %r14 function %rotr_i8_imm(i8) -> i8 { @@ -529,9 +529,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r3, %v1, 1 -; nill %r3, 31 -; srlk %r2, %r2, 0(%r3) +; vlgvg %r4, %v1, 1 +; nill %r4, 31 +; srlk %r2, %r2, 0(%r4) ; br %r14 function %ushr_i32_reg(i32, i32) -> i32 { @@ -565,9 +565,9 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llhr %r3, %r2 -; vlgvg %r5, %v1, 1 -; nill %r5, 15 -; srlk %r2, %r3, 0(%r5) +; vlgvg %r2, %v1, 1 +; nill %r2, 15 +; srlk %r2, %r3, 0(%r2) ; br %r14 function %ushr_i16_reg(i16, i16) -> i16 { @@ -603,9 +603,9 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) ; llcr %r3, %r2 -; vlgvg %r5, %v1, 1 -; nill %r5, 7 -; srlk %r2, %r3, 0(%r5) +; vlgvg %r2, %v1, 1 +; nill %r2, 7 +; srlk %r2, %r3, 0(%r2) ; br %r14 function %ushr_i8_reg(i8, i8) -> i8 { @@ -718,9 +718,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r3, %v1, 1 -; nill %r3, 31 -; sllk %r2, %r2, 0(%r3) +; vlgvg %r4, %v1, 1 +; nill %r4, 31 +; sllk %r2, %r2, 0(%r4) ; br %r14 function %ishl_i32_reg(i32, i32) -> i32 { @@ -753,9 +753,9 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r3, %v1, 1 -; nill %r3, 15 -; sllk %r2, %r2, 0(%r3) +; vlgvg %r4, %v1, 1 +; nill %r4, 15 +; sllk %r2, %r2, 0(%r4) ; br %r14 function %ishl_i16_reg(i16, i16) -> i16 { @@ -788,9 +788,9 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r3, %v1, 1 -; nill %r3, 7 -; sllk %r2, %r2, 0(%r3) +; vlgvg %r4, %v1, 1 +; nill %r4, 7 +; sllk %r2, %r2, 0(%r4) ; br %r14 function %ishl_i8_reg(i8, i8) -> i8 { @@ -901,9 +901,9 @@ block0(v0: i32, v1: i128): ; block0: ; vl %v1, 0(%r3) -; vlgvg %r3, %v1, 1 -; nill %r3, 31 -; srak %r2, %r2, 0(%r3) +; vlgvg %r4, %v1, 1 +; nill %r4, 31 +; srak %r2, %r2, 0(%r4) ; br %r14 function %sshr_i32_reg(i32, i32) -> i32 { @@ -937,9 +937,9 @@ block0(v0: i16, v1: i128): ; block0: ; vl %v1, 0(%r3) ; lhr %r3, %r2 -; vlgvg %r5, %v1, 1 -; nill %r5, 15 -; srak %r2, %r3, 0(%r5) +; vlgvg %r2, %v1, 1 +; nill %r2, 15 +; srak %r2, %r3, 0(%r2) ; br %r14 function %sshr_i16_reg(i16, i16) -> i16 { @@ -975,9 +975,9 @@ block0(v0: i8, v1: i128): ; block0: ; vl %v1, 0(%r3) ; lbr %r3, %r2 -; vlgvg %r5, %v1, 1 -; nill %r5, 7 -; srak %r2, %r3, 0(%r5) +; vlgvg %r2, %v1, 1 +; nill %r2, 7 +; srak %r2, %r3, 0(%r2) ; br %r14 function %sshr_i8_reg(i8, i8) -> i8 {