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Rewrite as iterator methods

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Copyright (c) 2021, Arm Limited
This commit is contained in:
dheaton-arm
2021-09-09 10:31:23 +01:00
parent 5824cca0f8
commit 924b0368e9
1 changed files with 10 additions and 14 deletions
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24
cranelift/interpreter/src/step.rs
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@@ -826,24 +826,20 @@ where
Opcode::SwidenHigh => unimplemented!("SwidenHigh"), Opcode::SwidenHigh => unimplemented!("SwidenHigh"),
Opcode::UwidenLow => { Opcode::UwidenLow => {
let new_type = ctrl_ty.merge_lanes().unwrap(); let new_type = ctrl_ty.merge_lanes().unwrap();
let mut new_vec = SimdVec::new(); let new_vec = extractlanes(&arg(0)?, ctrl_ty.lane_type())?
let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?; .into_iter()
arg0.truncate(new_type.lane_count() as usize); .take(new_type.lane_count() as usize)
for lane in arg0 { .map(|lane| lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type())))
let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?; .collect::<ValueResult<Vec<_>>>()?;
new_vec.push(lane);
}
assign(vectorizelanes(&new_vec, new_type)?) assign(vectorizelanes(&new_vec, new_type)?)
} }
Opcode::UwidenHigh => { Opcode::UwidenHigh => {
let new_type = ctrl_ty.merge_lanes().unwrap(); let new_type = ctrl_ty.merge_lanes().unwrap();
let mut new_vec = SimdVec::new(); let new_vec = extractlanes(&arg(0)?, ctrl_ty.lane_type())?
let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?; .into_iter()
arg0.drain(0..new_type.lane_count() as usize); .skip(new_type.lane_count() as usize)
for lane in arg0 { .map(|lane| lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type())))
let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?; .collect::<ValueResult<Vec<_>>>()?;
new_vec.push(lane);
}
assign(vectorizelanes(&new_vec, new_type)?) assign(vectorizelanes(&new_vec, new_type)?)
} }
Opcode::FcvtToUint => unimplemented!("FcvtToUint"), Opcode::FcvtToUint => unimplemented!("FcvtToUint"),