From 924b0368e9b18bf9d32d52b95878704059ac99d0 Mon Sep 17 00:00:00 2001 From: dheaton-arm Date: Thu, 9 Sep 2021 10:31:23 +0100 Subject: [PATCH] Rewrite as iterator methods Copyright (c) 2021, Arm Limited --- cranelift/interpreter/src/step.rs | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/cranelift/interpreter/src/step.rs b/cranelift/interpreter/src/step.rs index c5cdd82fa3..eb519d2e08 100644 --- a/cranelift/interpreter/src/step.rs +++ b/cranelift/interpreter/src/step.rs @@ -826,24 +826,20 @@ where Opcode::SwidenHigh => unimplemented!("SwidenHigh"), Opcode::UwidenLow => { let new_type = ctrl_ty.merge_lanes().unwrap(); - let mut new_vec = SimdVec::new(); - let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?; - arg0.truncate(new_type.lane_count() as usize); - for lane in arg0 { - let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?; - new_vec.push(lane); - } + let new_vec = extractlanes(&arg(0)?, ctrl_ty.lane_type())? + .into_iter() + .take(new_type.lane_count() as usize) + .map(|lane| lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))) + .collect::>>()?; assign(vectorizelanes(&new_vec, new_type)?) } Opcode::UwidenHigh => { let new_type = ctrl_ty.merge_lanes().unwrap(); - let mut new_vec = SimdVec::new(); - let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?; - arg0.drain(0..new_type.lane_count() as usize); - for lane in arg0 { - let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?; - new_vec.push(lane); - } + let new_vec = extractlanes(&arg(0)?, ctrl_ty.lane_type())? + .into_iter() + .skip(new_type.lane_count() as usize) + .map(|lane| lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))) + .collect::>>()?; assign(vectorizelanes(&new_vec, new_type)?) } Opcode::FcvtToUint => unimplemented!("FcvtToUint"),