[meta] Move x86 settings generation to their own file;
This commit is contained in:
Benjamin Bouvier
@@ -1,7 +1,6 @@
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use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
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use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
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use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
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use crate::shared::types::Bool::B1;
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use crate::shared::types::Bool::B1;
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use crate::shared::types::Float::{F32, F64};
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use crate::shared::types::Float::{F32, F64};
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@@ -10,92 +9,7 @@ use crate::shared::Definitions as SharedDefinitions;
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mod instructions;
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mod instructions;
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mod legalize;
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mod legalize;
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mod settings;
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fn define_settings(shared: &SettingGroup) -> SettingGroup {
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let mut settings = SettingGroupBuilder::new("x86");
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// CPUID.01H:ECX
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let has_sse3 = settings.add_bool("has_sse3", "SSE3: CPUID.01H:ECX.SSE3[bit 0]", false);
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let has_ssse3 = settings.add_bool("has_ssse3", "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]", false);
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let has_sse41 = settings.add_bool("has_sse41", "SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]", false);
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let has_sse42 = settings.add_bool("has_sse42", "SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]", false);
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let has_popcnt = settings.add_bool("has_popcnt", "POPCNT: CPUID.01H:ECX.POPCNT[bit 23]", false);
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settings.add_bool("has_avx", "AVX: CPUID.01H:ECX.AVX[bit 28]", false);
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// CPUID.(EAX=07H, ECX=0H):EBX
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let has_bmi1 = settings.add_bool(
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"has_bmi1",
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"BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
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false,
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);
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let has_bmi2 = settings.add_bool(
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"has_bmi2",
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"BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
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false,
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);
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// CPUID.EAX=80000001H:ECX
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let has_lzcnt = settings.add_bool(
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"has_lzcnt",
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"LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
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false,
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);
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settings.add_predicate("use_sse41", predicate!(has_sse41));
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settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
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settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
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settings.add_predicate("use_bmi1", predicate!(has_bmi1));
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settings.add_predicate("use_lznct", predicate!(has_lzcnt));
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// Some shared boolean values are used in x86 instruction predicates, so we need to group them
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// in the same TargetIsa, for compabitibity with code generated by meta-python.
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// TODO Once all the meta generation code has been migrated from Python to Rust, we can put it
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// back in the shared SettingGroup, and use it in x86 instruction predicates.
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let is_pic = shared.get_bool("is_pic");
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let allones_funcaddrs = shared.get_bool("allones_funcaddrs");
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settings.add_predicate("is_pic", predicate!(is_pic));
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settings.add_predicate("not_is_pic", predicate!(!is_pic));
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settings.add_predicate(
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"all_ones_funcaddrs_and_not_is_pic",
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predicate!(allones_funcaddrs && !is_pic),
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);
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settings.add_predicate(
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"not_all_ones_funcaddrs_and_not_is_pic",
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predicate!(!allones_funcaddrs && !is_pic),
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);
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// Presets corresponding to x86 CPUs.
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settings.add_preset("baseline", preset!());
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let nehalem = settings.add_preset(
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"nehalem",
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preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
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);
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let haswell = settings.add_preset(
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"haswell",
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preset!(nehalem && has_bmi1 && has_bmi2 && has_lzcnt),
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);
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let broadwell = settings.add_preset("broadwell", preset!(haswell));
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let skylake = settings.add_preset("skylake", preset!(broadwell));
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let cannonlake = settings.add_preset("cannonlake", preset!(skylake));
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settings.add_preset("icelake", preset!(cannonlake));
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settings.add_preset(
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"znver1",
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preset!(
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has_sse3
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&& has_ssse3
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&& has_sse41
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&& has_sse42
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&& has_popcnt
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&& has_bmi1
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&& has_bmi2
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&& has_lzcnt
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),
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);
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settings.finish()
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}
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fn define_registers() -> IsaRegs {
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fn define_registers() -> IsaRegs {
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let mut regs = IsaRegsBuilder::new();
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let mut regs = IsaRegsBuilder::new();
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@@ -139,7 +53,7 @@ fn define_registers() -> IsaRegs {
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}
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}
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pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = define_settings(&shared_defs.settings);
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let settings = settings::define(&shared_defs.settings);
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let regs = define_registers();
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let regs = define_registers();
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let inst_group = instructions::define(&shared_defs.format_registry);
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let inst_group = instructions::define(&shared_defs.format_registry);
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87
cranelift/codegen/meta/src/isa/x86/settings.rs
Normal file
87
cranelift/codegen/meta/src/isa/x86/settings.rs
Normal file
@@ -0,0 +1,87 @@
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use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
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pub fn define(shared: &SettingGroup) -> SettingGroup {
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let mut settings = SettingGroupBuilder::new("x86");
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// CPUID.01H:ECX
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let has_sse3 = settings.add_bool("has_sse3", "SSE3: CPUID.01H:ECX.SSE3[bit 0]", false);
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let has_ssse3 = settings.add_bool("has_ssse3", "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]", false);
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let has_sse41 = settings.add_bool("has_sse41", "SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]", false);
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let has_sse42 = settings.add_bool("has_sse42", "SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]", false);
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let has_popcnt = settings.add_bool("has_popcnt", "POPCNT: CPUID.01H:ECX.POPCNT[bit 23]", false);
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settings.add_bool("has_avx", "AVX: CPUID.01H:ECX.AVX[bit 28]", false);
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// CPUID.(EAX=07H, ECX=0H):EBX
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let has_bmi1 = settings.add_bool(
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"has_bmi1",
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"BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
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false,
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);
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let has_bmi2 = settings.add_bool(
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"has_bmi2",
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"BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
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false,
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);
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// CPUID.EAX=80000001H:ECX
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let has_lzcnt = settings.add_bool(
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"has_lzcnt",
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"LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
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false,
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);
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settings.add_predicate("use_sse41", predicate!(has_sse41));
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settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
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settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
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settings.add_predicate("use_bmi1", predicate!(has_bmi1));
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settings.add_predicate("use_lznct", predicate!(has_lzcnt));
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// Some shared boolean values are used in x86 instruction predicates, so we need to group them
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// in the same TargetIsa, for compabitibity with code generated by meta-python.
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// TODO Once all the meta generation code has been migrated from Python to Rust, we can put it
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// back in the shared SettingGroup, and use it in x86 instruction predicates.
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let is_pic = shared.get_bool("is_pic");
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let allones_funcaddrs = shared.get_bool("allones_funcaddrs");
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settings.add_predicate("is_pic", predicate!(is_pic));
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settings.add_predicate("not_is_pic", predicate!(!is_pic));
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settings.add_predicate(
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"all_ones_funcaddrs_and_not_is_pic",
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predicate!(allones_funcaddrs && !is_pic),
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);
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settings.add_predicate(
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"not_all_ones_funcaddrs_and_not_is_pic",
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predicate!(!allones_funcaddrs && !is_pic),
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);
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// Presets corresponding to x86 CPUs.
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settings.add_preset("baseline", preset!());
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let nehalem = settings.add_preset(
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"nehalem",
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preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
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);
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let haswell = settings.add_preset(
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"haswell",
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preset!(nehalem && has_bmi1 && has_bmi2 && has_lzcnt),
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);
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let broadwell = settings.add_preset("broadwell", preset!(haswell));
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let skylake = settings.add_preset("skylake", preset!(broadwell));
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let cannonlake = settings.add_preset("cannonlake", preset!(skylake));
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settings.add_preset("icelake", preset!(cannonlake));
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settings.add_preset(
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"znver1",
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preset!(
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has_sse3
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&& has_ssse3
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&& has_sse41
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&& has_sse42
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&& has_popcnt
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&& has_bmi1
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&& has_bmi2
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&& has_lzcnt
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),
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);
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settings.finish()
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}
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