diff --git a/cranelift/codegen/meta/src/isa/x86/mod.rs b/cranelift/codegen/meta/src/isa/x86/mod.rs
index 861553bf88..bf59b8d9c1 100644
--- a/cranelift/codegen/meta/src/isa/x86/mod.rs
+++ b/cranelift/codegen/meta/src/isa/x86/mod.rs
@@ -1,7 +1,6 @@
 use crate::cdsl::cpu_modes::CpuMode;
 use crate::cdsl::isa::TargetIsa;
 use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
-use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
 
 use crate::shared::types::Bool::B1;
 use crate::shared::types::Float::{F32, F64};
@@ -10,92 +9,7 @@ use crate::shared::Definitions as SharedDefinitions;
 
 mod instructions;
 mod legalize;
-
-fn define_settings(shared: &SettingGroup) -> SettingGroup {
-    let mut settings = SettingGroupBuilder::new("x86");
-
-    // CPUID.01H:ECX
-    let has_sse3 = settings.add_bool("has_sse3", "SSE3: CPUID.01H:ECX.SSE3[bit 0]", false);
-    let has_ssse3 = settings.add_bool("has_ssse3", "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]", false);
-    let has_sse41 = settings.add_bool("has_sse41", "SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]", false);
-    let has_sse42 = settings.add_bool("has_sse42", "SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]", false);
-    let has_popcnt = settings.add_bool("has_popcnt", "POPCNT: CPUID.01H:ECX.POPCNT[bit 23]", false);
-    settings.add_bool("has_avx", "AVX: CPUID.01H:ECX.AVX[bit 28]", false);
-
-    // CPUID.(EAX=07H, ECX=0H):EBX
-    let has_bmi1 = settings.add_bool(
-        "has_bmi1",
-        "BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
-        false,
-    );
-    let has_bmi2 = settings.add_bool(
-        "has_bmi2",
-        "BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
-        false,
-    );
-
-    // CPUID.EAX=80000001H:ECX
-    let has_lzcnt = settings.add_bool(
-        "has_lzcnt",
-        "LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
-        false,
-    );
-
-    settings.add_predicate("use_sse41", predicate!(has_sse41));
-    settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
-    settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
-    settings.add_predicate("use_bmi1", predicate!(has_bmi1));
-    settings.add_predicate("use_lznct", predicate!(has_lzcnt));
-
-    // Some shared boolean values are used in x86 instruction predicates, so we need to group them
-    // in the same TargetIsa, for compabitibity with code generated by meta-python.
-    // TODO Once all the meta generation code has been migrated from Python to Rust, we can put it
-    // back in the shared SettingGroup, and use it in x86 instruction predicates.
-
-    let is_pic = shared.get_bool("is_pic");
-    let allones_funcaddrs = shared.get_bool("allones_funcaddrs");
-    settings.add_predicate("is_pic", predicate!(is_pic));
-    settings.add_predicate("not_is_pic", predicate!(!is_pic));
-    settings.add_predicate(
-        "all_ones_funcaddrs_and_not_is_pic",
-        predicate!(allones_funcaddrs && !is_pic),
-    );
-    settings.add_predicate(
-        "not_all_ones_funcaddrs_and_not_is_pic",
-        predicate!(!allones_funcaddrs && !is_pic),
-    );
-
-    // Presets corresponding to x86 CPUs.
-
-    settings.add_preset("baseline", preset!());
-    let nehalem = settings.add_preset(
-        "nehalem",
-        preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
-    );
-    let haswell = settings.add_preset(
-        "haswell",
-        preset!(nehalem && has_bmi1 && has_bmi2 && has_lzcnt),
-    );
-    let broadwell = settings.add_preset("broadwell", preset!(haswell));
-    let skylake = settings.add_preset("skylake", preset!(broadwell));
-    let cannonlake = settings.add_preset("cannonlake", preset!(skylake));
-    settings.add_preset("icelake", preset!(cannonlake));
-    settings.add_preset(
-        "znver1",
-        preset!(
-            has_sse3
-                && has_ssse3
-                && has_sse41
-                && has_sse42
-                && has_popcnt
-                && has_bmi1
-                && has_bmi2
-                && has_lzcnt
-        ),
-    );
-
-    settings.finish()
-}
+mod settings;
 
 fn define_registers() -> IsaRegs {
     let mut regs = IsaRegsBuilder::new();
@@ -139,7 +53,7 @@ fn define_registers() -> IsaRegs {
 }
 
 pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
-    let settings = define_settings(&shared_defs.settings);
+    let settings = settings::define(&shared_defs.settings);
     let regs = define_registers();
 
     let inst_group = instructions::define(&shared_defs.format_registry);
diff --git a/cranelift/codegen/meta/src/isa/x86/settings.rs b/cranelift/codegen/meta/src/isa/x86/settings.rs
new file mode 100644
index 0000000000..f9b1908d11
--- /dev/null
+++ b/cranelift/codegen/meta/src/isa/x86/settings.rs
@@ -0,0 +1,87 @@
+use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
+
+pub fn define(shared: &SettingGroup) -> SettingGroup {
+    let mut settings = SettingGroupBuilder::new("x86");
+
+    // CPUID.01H:ECX
+    let has_sse3 = settings.add_bool("has_sse3", "SSE3: CPUID.01H:ECX.SSE3[bit 0]", false);
+    let has_ssse3 = settings.add_bool("has_ssse3", "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]", false);
+    let has_sse41 = settings.add_bool("has_sse41", "SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]", false);
+    let has_sse42 = settings.add_bool("has_sse42", "SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]", false);
+    let has_popcnt = settings.add_bool("has_popcnt", "POPCNT: CPUID.01H:ECX.POPCNT[bit 23]", false);
+    settings.add_bool("has_avx", "AVX: CPUID.01H:ECX.AVX[bit 28]", false);
+
+    // CPUID.(EAX=07H, ECX=0H):EBX
+    let has_bmi1 = settings.add_bool(
+        "has_bmi1",
+        "BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
+        false,
+    );
+    let has_bmi2 = settings.add_bool(
+        "has_bmi2",
+        "BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
+        false,
+    );
+
+    // CPUID.EAX=80000001H:ECX
+    let has_lzcnt = settings.add_bool(
+        "has_lzcnt",
+        "LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
+        false,
+    );
+
+    settings.add_predicate("use_sse41", predicate!(has_sse41));
+    settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
+    settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
+    settings.add_predicate("use_bmi1", predicate!(has_bmi1));
+    settings.add_predicate("use_lznct", predicate!(has_lzcnt));
+
+    // Some shared boolean values are used in x86 instruction predicates, so we need to group them
+    // in the same TargetIsa, for compabitibity with code generated by meta-python.
+    // TODO Once all the meta generation code has been migrated from Python to Rust, we can put it
+    // back in the shared SettingGroup, and use it in x86 instruction predicates.
+
+    let is_pic = shared.get_bool("is_pic");
+    let allones_funcaddrs = shared.get_bool("allones_funcaddrs");
+    settings.add_predicate("is_pic", predicate!(is_pic));
+    settings.add_predicate("not_is_pic", predicate!(!is_pic));
+    settings.add_predicate(
+        "all_ones_funcaddrs_and_not_is_pic",
+        predicate!(allones_funcaddrs && !is_pic),
+    );
+    settings.add_predicate(
+        "not_all_ones_funcaddrs_and_not_is_pic",
+        predicate!(!allones_funcaddrs && !is_pic),
+    );
+
+    // Presets corresponding to x86 CPUs.
+
+    settings.add_preset("baseline", preset!());
+    let nehalem = settings.add_preset(
+        "nehalem",
+        preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
+    );
+    let haswell = settings.add_preset(
+        "haswell",
+        preset!(nehalem && has_bmi1 && has_bmi2 && has_lzcnt),
+    );
+    let broadwell = settings.add_preset("broadwell", preset!(haswell));
+    let skylake = settings.add_preset("skylake", preset!(broadwell));
+    let cannonlake = settings.add_preset("cannonlake", preset!(skylake));
+    settings.add_preset("icelake", preset!(cannonlake));
+    settings.add_preset(
+        "znver1",
+        preset!(
+            has_sse3
+                && has_ssse3
+                && has_sse41
+                && has_sse42
+                && has_popcnt
+                && has_bmi1
+                && has_bmi2
+                && has_lzcnt
+        ),
+    );
+
+    settings.finish()
+}