Intel encodings for trap.

Use a ud2 instruction which generates an undefined instruction
exception.

lib/cretonne/meta/isa/intel/encodings.py

@@ -175,6 +175,12 @@ I64.enc(base.brnz.i64, *r.tjccb.rex(0x75, w=1))
 I64.enc(base.brnz.i32, *r.tjccb.rex(0x75))
 I64.enc(base.brnz.i32, *r.tjccb(0x75))
 
+#
+# Trap as ud2
+#
+I32.enc(base.trap, *r.noop(0x0f, 0x0b))
+I64.enc(base.trap, *r.noop(0x0f, 0x0b))
+
 #
 # Comparisons
 #

lib/cretonne/meta/isa/intel/recipes.py

@@ -5,7 +5,7 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
-from base.formats import Call, IndirectCall, Store, Load
+from base.formats import Nullary, Call, IndirectCall, Store, Load
 from base.formats import IntCompare
 from base.formats import RegMove, Ternary, Jump, Branch
 from .registers import GPR, ABCD
@@ -194,6 +194,11 @@ class TailRecipe:
 # copies and no-op conversions.
 null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
 
+# XX opcode, no ModR/M.
+noop = TailRecipe(
+        'noop', Nullary, size=0, ins=(), outs=(),
+        emit='PUT_OP(bits, 0, sink);')
+
 # XX /r
 rr = TailRecipe(
         'rr', Binary, size=1, ins=(GPR, GPR), outs=0,