From 87c5f27ff7c24b3b30495c940572e2d68a956252 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Wed, 19 Jul 2017 15:01:32 -0700
Subject: [PATCH] Intel encodings for trap.

Use a ud2 instruction which generates an undefined instruction
exception.
---
 cranelift/filetests/isa/intel/binary32.cton | 2 +-
 cranelift/filetests/isa/intel/binary64.cton | 2 +-
 cranelift/filetests/wasm/control.cton       | 5 +++++
 lib/cretonne/meta/isa/intel/encodings.py    | 6 ++++++
 lib/cretonne/meta/isa/intel/recipes.py      | 7 ++++++-
 5 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 7e95f84818..456623a235 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -364,5 +364,5 @@ ebb1:
 
     ; asm: ebb2:
 ebb2:
-    jump ebb1                                   ; bin: eb fd
+    trap                                        ; bin: 0f 0b
 }
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 3e332e2175..3d93ba86ec 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -626,5 +626,5 @@ ebb0:
     ; asm: movl %r10d, %ecx
     [-,%rcx]            v32 = uextend.i64 v13           ; bin: 44 89 d1
 
-    return
+    trap                                                ; bin: 0f 0b
 }
diff --git a/cranelift/filetests/wasm/control.cton b/cranelift/filetests/wasm/control.cton
index 0e82b05245..c8e37a536f 100644
--- a/cranelift/filetests/wasm/control.cton
+++ b/cranelift/filetests/wasm/control.cton
@@ -43,3 +43,8 @@ ebb0(v0: i32):
 ebb1(v2: i32):
     return v2
 }
+
+function %undefined() {
+ebb0:
+    trap
+}
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 16074cd849..fcf114ef3e 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -175,6 +175,12 @@ I64.enc(base.brnz.i64, *r.tjccb.rex(0x75, w=1))
 I64.enc(base.brnz.i32, *r.tjccb.rex(0x75))
 I64.enc(base.brnz.i32, *r.tjccb(0x75))
 
+#
+# Trap as ud2
+#
+I32.enc(base.trap, *r.noop(0x0f, 0x0b))
+I64.enc(base.trap, *r.noop(0x0f, 0x0b))
+
 #
 # Comparisons
 #
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 5ff1e8b225..efffc47319 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -5,7 +5,7 @@ from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
 from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
-from base.formats import Call, IndirectCall, Store, Load
+from base.formats import Nullary, Call, IndirectCall, Store, Load
 from base.formats import IntCompare
 from base.formats import RegMove, Ternary, Jump, Branch
 from .registers import GPR, ABCD
@@ -194,6 +194,11 @@ class TailRecipe:
 # copies and no-op conversions.
 null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
 
+# XX opcode, no ModR/M.
+noop = TailRecipe(
+        'noop', Nullary, size=0, ins=(), outs=(),
+        emit='PUT_OP(bits, 0, sink);')
+
 # XX /r
 rr = TailRecipe(
         'rr', Binary, size=1, ins=(GPR, GPR), outs=0,