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Add RISC-V encodings for b1 copy/spill/fill.

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We allow b1 values in general purpose registers, so we need to be able
to move them around.
This commit is contained in:
Jakob Stoklund Olesen
2018-01-12 11:11:49 -08:00
parent 567e570c02
commit 85aab278dd
1 changed files with 5 additions and 0 deletions
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5
lib/cretonne/meta/isa/riscv/encodings.py
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@@ -155,3 +155,8 @@ RV64.enc(base.copy.i32, Icopy, OPIMM32(0b000))
RV32.enc(base.regmove.i32, Irmov, OPIMM(0b000)) RV32.enc(base.regmove.i32, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.i64, Irmov, OPIMM(0b000)) RV64.enc(base.regmove.i64, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.i32, Irmov, OPIMM32(0b000)) RV64.enc(base.regmove.i32, Irmov, OPIMM32(0b000))
RV32.enc(base.copy.b1, Icopy, OPIMM(0b000))
RV64.enc(base.copy.b1, Icopy, OPIMM(0b000))
RV32.enc(base.regmove.b1, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.b1, Irmov, OPIMM(0b000))