From 85aab278ddb451752d0b07b5fbef2d2931befdd8 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 12 Jan 2018 11:11:49 -0800 Subject: [PATCH] Add RISC-V encodings for b1 copy/spill/fill. We allow b1 values in general purpose registers, so we need to be able to move them around. --- lib/cretonne/meta/isa/riscv/encodings.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/cretonne/meta/isa/riscv/encodings.py b/lib/cretonne/meta/isa/riscv/encodings.py index ac719460a1..374aef17d1 100644 --- a/lib/cretonne/meta/isa/riscv/encodings.py +++ b/lib/cretonne/meta/isa/riscv/encodings.py @@ -155,3 +155,8 @@ RV64.enc(base.copy.i32, Icopy, OPIMM32(0b000)) RV32.enc(base.regmove.i32, Irmov, OPIMM(0b000)) RV64.enc(base.regmove.i64, Irmov, OPIMM(0b000)) RV64.enc(base.regmove.i32, Irmov, OPIMM32(0b000)) + +RV32.enc(base.copy.b1, Icopy, OPIMM(0b000)) +RV64.enc(base.copy.b1, Icopy, OPIMM(0b000)) +RV32.enc(base.regmove.b1, Irmov, OPIMM(0b000)) +RV64.enc(base.regmove.b1, Irmov, OPIMM(0b000))