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Remove some uses of riscv in tests (#2600)

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* Remove some uses of riscv in tests

* Fix typo

* Apply suggestions from code review

* Apply suggestions from code review

Co-authored-by: Benjamin Bouvier <public@benj.me>
This commit is contained in:
bjorn3
2021-01-30 23:54:48 +01:00
committed by GitHub
parent 3e38fb984a
commit 81b4e48f9f
3 changed files with 32 additions and 31 deletions
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7
cranelift/codegen/src/isa/mod.rs
View File

@@ -20,7 +20,6 @@
//! appropriate for the requested ISA:
//!
//! ```
//! # extern crate cranelift_codegen;
//! # #[macro_use] extern crate target_lexicon;
//! use cranelift_codegen::isa;
//! use cranelift_codegen::settings::{self, Configurable};
@@ -30,12 +29,12 @@
//! let shared_builder = settings::builder();
//! let shared_flags = settings::Flags::new(shared_builder);
//!
//! match isa::lookup(triple!("riscv32")) {
//! match isa::lookup(triple!("x86_64")) {
//! Err(_) => {
//! // The RISC-V target ISA is not available.
//! // The x86_64 target ISA is not available.
//! }
//! Ok(mut isa_builder) => {
//! isa_builder.set("supports_m", "on");
//! isa_builder.set("use_popcnt", "on");
//! let isa = isa_builder.finish(shared_flags);
//! }
//! }

46
cranelift/frontend/src/frontend.rs
View File

@@ -975,12 +975,12 @@ mod tests {
let shared_flags = settings::Flags::new(shared_builder);
let triple =
::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple");
::target_lexicon::Triple::from_str("x86_64").expect("Couldn't create x86_64 triple");
let target = isa::lookup(triple)
.ok()
.map(|b| b.finish(shared_flags))
.expect("This test requires riscv32 support.");
.expect("This test requires x86_64 support.");
let mut sig = Signature::new(target.default_call_conv());
sig.returns.push(AbiParam::new(I32));
@@ -1013,13 +1013,13 @@ mod tests {
assert_eq!(
func.display(None).to_string(),
"function %sample() -> i32 system_v {
sig0 = (i32, i32, i32) system_v
sig0 = (i64, i64, i64) system_v
fn0 = %Memcpy sig0
block0:
v3 = iconst.i32 0
v3 = iconst.i64 0
v1 -> v3
v2 = iconst.i32 0
v2 = iconst.i64 0
v0 -> v2
call fn0(v1, v0, v1)
return v1
@@ -1037,12 +1037,12 @@ block0:
let shared_flags = settings::Flags::new(shared_builder);
let triple =
::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple");
::target_lexicon::Triple::from_str("x86_64").expect("Couldn't create x86_64 triple");
let target = isa::lookup(triple)
.ok()
.map(|b| b.finish(shared_flags))
.expect("This test requires riscv32 support.");
.expect("This test requires x86_64 support.");
let mut sig = Signature::new(target.default_call_conv());
sig.returns.push(AbiParam::new(I32));
@@ -1074,9 +1074,9 @@ block0:
func.display(None).to_string(),
"function %sample() -> i32 system_v {
block0:
v4 = iconst.i32 0
v4 = iconst.i64 0
v1 -> v4
v3 = iconst.i32 0
v3 = iconst.i64 0
v0 -> v3
v2 = load.i64 aligned v0
store aligned v2, v1
@@ -1095,12 +1095,12 @@ block0:
let shared_flags = settings::Flags::new(shared_builder);
let triple =
::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple");
::target_lexicon::Triple::from_str("x86_64").expect("Couldn't create x86_64 triple");
let target = isa::lookup(triple)
.ok()
.map(|b| b.finish(shared_flags))
.expect("This test requires riscv32 support.");
.expect("This test requires x86_64 support.");
let mut sig = Signature::new(target.default_call_conv());
sig.returns.push(AbiParam::new(I32));
@@ -1131,15 +1131,15 @@ block0:
assert_eq!(
func.display(None).to_string(),
"function %sample() -> i32 system_v {
sig0 = (i32, i32, i32) system_v
sig0 = (i64, i64, i64) system_v
fn0 = %Memcpy sig0
block0:
v4 = iconst.i32 0
v4 = iconst.i64 0
v1 -> v4
v3 = iconst.i32 0
v3 = iconst.i64 0
v0 -> v3
v2 = iconst.i32 8192
v2 = iconst.i64 8192
call fn0(v1, v0, v2)
return v1
}
@@ -1156,12 +1156,12 @@ block0:
let shared_flags = settings::Flags::new(shared_builder);
let triple =
::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple");
::target_lexicon::Triple::from_str("x86_64").expect("Couldn't create x86_64 triple");
let target = isa::lookup(triple)
.ok()
.map(|b| b.finish(shared_flags))
.expect("This test requires riscv32 support.");
.expect("This test requires x86_64 support.");
let mut sig = Signature::new(target.default_call_conv());
sig.returns.push(AbiParam::new(I32));
@@ -1190,7 +1190,7 @@ block0:
func.display(None).to_string(),
"function %sample() -> i32 system_v {
block0:
v2 = iconst.i32 0
v2 = iconst.i64 0
v0 -> v2
v1 = iconst.i64 0x0001_0001_0101
store aligned v1, v0
@@ -1209,12 +1209,12 @@ block0:
let shared_flags = settings::Flags::new(shared_builder);
let triple =
::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple");
::target_lexicon::Triple::from_str("x86_64").expect("Couldn't create x86_64 triple");
let target = isa::lookup(triple)
.ok()
.map(|b| b.finish(shared_flags))
.expect("This test requires riscv32 support.");
.expect("This test requires x86_64 support.");
let mut sig = Signature::new(target.default_call_conv());
sig.returns.push(AbiParam::new(I32));
@@ -1242,14 +1242,14 @@ block0:
assert_eq!(
func.display(None).to_string(),
"function %sample() -> i32 system_v {
sig0 = (i32, i32, i32) system_v
sig0 = (i64, i32, i64) system_v
fn0 = %Memset sig0
block0:
v4 = iconst.i32 0
v4 = iconst.i64 0
v0 -> v4
v1 = iconst.i8 1
v2 = iconst.i32 8192
v2 = iconst.i64 8192
v3 = uextend.i32 v1
call fn0(v0, v3, v2)
return v0

10
cranelift/reader/src/parser.rs
View File

@@ -3678,7 +3678,6 @@ mod tests {
}
#[test]
#[cfg(feature = "riscv")]
fn isa_spec() {
assert!(parse_test(
"target
@@ -3688,7 +3687,7 @@ mod tests {
.is_err());
assert!(parse_test(
"target riscv32
"target x86_64
set enable_float=false
function %foo() system_v {}",
ParseOptions::default()
@@ -3697,7 +3696,7 @@ mod tests {
match parse_test(
"set enable_float=false
isa riscv
target x86_64
function %foo() system_v {}",
ParseOptions::default(),
)
@@ -3707,7 +3706,10 @@ mod tests {
IsaSpec::None(_) => panic!("Expected some ISA"),
IsaSpec::Some(v) => {
assert_eq!(v.len(), 1);
assert_eq!(v[0].name(), "riscv");
#[cfg(not(feature = "experimental_x64"))]
assert_eq!(v[0].name(), "x86");
#[cfg(feature = "experimental_x64")]
assert_eq!(v[0].name(), "x64");
}
}
}