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fix issue #5497 #5524 #5526. (#5595)

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* fix issue 5497.

* fix issue 5524

* fix issue 5497 5524 5526.

* some clif change because of reg alloc.
This commit is contained in:
yuyang
2023-01-21 06:06:26 +08:00
committed by GitHub
parent 86790d36df
commit 7e10bd1f58
10 changed files with 150 additions and 26 deletions
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3
cranelift/codegen/src/isa/riscv64/inst/emit.rs
View File

@@ -1606,12 +1606,11 @@ impl MachInstEmit for Inst {
val: &ValueRegs<Reg>,
sink: &mut MachBuffer<Inst>,
state: &mut EmitState| {
let ty = if ty.bits() == 128 { I64 } else { ty };
let mut insts = SmallInstVec::new();
insts.push(Inst::Mov {
rd: dst[0],
rm: val.regs()[0],
ty,
ty: I64,
});
if ty.bits() == 128 {
insts.push(Inst::Mov {

10
cranelift/codegen/src/isa/riscv64/inst/mod.rs
View File

@@ -464,7 +464,9 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_use(condition);
collector.reg_uses(x.regs());
collector.reg_uses(y.regs());
collector.reg_defs(&dst[..]);
for d in dst.iter() {
collector.reg_early_def(d.clone());
}
}
&Inst::ReferenceCheck { rd, x, .. } => {
collector.reg_use(x);
@@ -491,7 +493,9 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
} => {
collector.reg_uses(x.regs());
collector.reg_uses(y.regs());
collector.reg_defs(&dst[..]);
for d in dst.iter() {
collector.reg_early_def(d.clone());
}
}
&Inst::Csr { rd, rs, .. } => {
@@ -534,7 +538,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_use(test);
collector.reg_uses(x.regs());
collector.reg_uses(y.regs());
rd.iter().for_each(|r| collector.reg_def(*r));
rd.iter().for_each(|r| collector.reg_early_def(*r));
}
&Inst::RawData { .. } => {}
&Inst::AtomicStore { src, p, .. } => {