diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs index 36bdc2aa70..4bdb66c7c9 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs @@ -1606,12 +1606,11 @@ impl MachInstEmit for Inst { val: &ValueRegs, sink: &mut MachBuffer, state: &mut EmitState| { - let ty = if ty.bits() == 128 { I64 } else { ty }; let mut insts = SmallInstVec::new(); insts.push(Inst::Mov { rd: dst[0], rm: val.regs()[0], - ty, + ty: I64, }); if ty.bits() == 128 { insts.push(Inst::Mov { diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs index 64f2e5a5d6..1f759a9b55 100644 --- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs +++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs @@ -464,7 +464,9 @@ fn riscv64_get_operands VReg>(inst: &Inst, collector: &mut Operan collector.reg_use(condition); collector.reg_uses(x.regs()); collector.reg_uses(y.regs()); - collector.reg_defs(&dst[..]); + for d in dst.iter() { + collector.reg_early_def(d.clone()); + } } &Inst::ReferenceCheck { rd, x, .. } => { collector.reg_use(x); @@ -491,7 +493,9 @@ fn riscv64_get_operands VReg>(inst: &Inst, collector: &mut Operan } => { collector.reg_uses(x.regs()); collector.reg_uses(y.regs()); - collector.reg_defs(&dst[..]); + for d in dst.iter() { + collector.reg_early_def(d.clone()); + } } &Inst::Csr { rd, rs, .. } => { @@ -534,7 +538,7 @@ fn riscv64_get_operands VReg>(inst: &Inst, collector: &mut Operan collector.reg_use(test); collector.reg_uses(x.regs()); collector.reg_uses(y.regs()); - rd.iter().for_each(|r| collector.reg_def(*r)); + rd.iter().for_each(|r| collector.reg_early_def(*r)); } &Inst::RawData { .. } => {} &Inst::AtomicStore { src, p, .. } => { diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif index baa894f28f..951b808d61 100644 --- a/cranelift/filetests/filetests/isa/riscv64/condops.clif +++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif @@ -77,7 +77,8 @@ block0(v0: i8, v1: i128, v2: i128): } ; block0: +; mv a7,a1 ; andi a5,a0,255 -; select_i128 [a0,a1],[a1,a2],[a3,a4]##condition=a5 +; select_i128 [a0,a1],[a7,a2],[a3,a4]##condition=a5 ; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat index bb4b66f545..fd74f5bae2 100644 --- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat +++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat @@ -45,8 +45,8 @@ ;; addi a5,a5,4092 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; sw a1,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; sw a1,0(t4) ;; j label1 ;; block1: ;; ret @@ -59,8 +59,8 @@ ;; addi a5,a5,4092 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; lw a0,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; lw a0,0(t4) ;; j label1 ;; block1: -;; ret \ No newline at end of file +;; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat index 37f86c7620..d98101b572 100644 --- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat +++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat @@ -45,8 +45,8 @@ ;; addi a5,a5,4095 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; sb a1,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; sb a1,0(t4) ;; j label1 ;; block1: ;; ret @@ -59,8 +59,8 @@ ;; addi a5,a5,4095 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; lbu a0,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; lbu a0,0(t4) ;; j label1 ;; block1: -;; ret \ No newline at end of file +;; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat index dd24c07a1e..ba3a160655 100644 --- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat +++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat @@ -45,8 +45,8 @@ ;; addi a5,a5,4092 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; sw a1,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; sw a1,0(t4) ;; j label1 ;; block1: ;; ret @@ -59,8 +59,8 @@ ;; addi a5,a5,4092 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; lw a0,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; lw a0,0(t4) ;; j label1 ;; block1: -;; ret \ No newline at end of file +;; ret diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat index ada4120532..82d8bbc052 100644 --- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat +++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat @@ -45,8 +45,8 @@ ;; addi a5,a5,4095 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; sb a1,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; sb a1,0(t4) ;; j label1 ;; block1: ;; ret @@ -59,8 +59,8 @@ ;; addi a5,a5,4095 ;; ugt t3,a0,a5##ty=i64 ;; li t0,0 -;; selectif_spectre_guard a7,t0,a7##test=t3 -;; lbu a0,0(a7) +;; selectif_spectre_guard t4,t0,a7##test=t3 +;; lbu a0,0(t4) ;; j label1 ;; block1: -;; ret \ No newline at end of file +;; ret diff --git a/cranelift/filetests/filetests/runtests/issue5497.clif b/cranelift/filetests/filetests/runtests/issue5497.clif new file mode 100644 index 0000000000..d035d40aa6 --- /dev/null +++ b/cranelift/filetests/filetests/runtests/issue5497.clif @@ -0,0 +1,11 @@ +test interpret +test run +target riscv64 + +function %a(i16, i128) -> i128 system_v { +block0(v0: i16, v1: i128): + v2 = smin v1, v1 + return v2 +} + +; run: %a(0, 1) == 1 \ No newline at end of file diff --git a/cranelift/filetests/filetests/runtests/issue5524.clif b/cranelift/filetests/filetests/runtests/issue5524.clif new file mode 100644 index 0000000000..3a8c1bd468 --- /dev/null +++ b/cranelift/filetests/filetests/runtests/issue5524.clif @@ -0,0 +1,11 @@ +test interpret +test run +target riscv64 + +function %a(i128, i8, i8, i8, i32, i32, i8, i8, i64, i8) -> i8, i8, i8, i128 system_v { +block0(v0: i128, v1: i8, v2: i8, v3: i8, v4: i32, v5: i32, v6: i8, v7: i8, v8: i64, v9: i8): + v16 = select v8, v0, v0 + return v1, v1, v1, v16 +} + +; run: %a(65280, 0, 0, 0, 0, 0, 0, 0, 0, 0) == [0, 0, 0, 65280] \ No newline at end of file diff --git a/cranelift/filetests/filetests/runtests/issue5526.clif b/cranelift/filetests/filetests/runtests/issue5526.clif new file mode 100644 index 0000000000..f91dec0fad --- /dev/null +++ b/cranelift/filetests/filetests/runtests/issue5526.clif @@ -0,0 +1,98 @@ +test interpret +test run +target riscv64 + +function %a(i128, i8, i8, i8, i16, i32, i8, i8, i64, i8) -> i8, i8, i8, i128, i8, i8, i64, i128, i8 system_v { + ss0 = explicit_slot 90 + ss1 = explicit_slot 90 + ss2 = explicit_slot 90 + ss3 = explicit_slot 90 + ss4 = explicit_slot 126 + ss5 = explicit_slot 126 + ss6 = explicit_slot 126 + ss7 = explicit_slot 126 + +block0(v0: i128, v1: i8, v2: i8, v3: i8, v4: i16, v5: i32, v6: i8, v7: i8, v8: i64, v9: i8): + v11 = iconst.i8 50 + v12 = iconst.i8 0 + v13 = iconst.i16 0 + v14 = iconst.i32 0 + v15 = iconst.i64 0 + v16 = uextend.i128 v15 ; v15 = 0 + stack_store v16, ss0 + stack_store v16, ss0+16 + stack_store v16, ss0+32 + stack_store v16, ss0+48 + stack_store v16, ss0+64 + stack_store v15, ss0+80 ; v15 = 0 + stack_store v13, ss0+88 ; v13 = 0 + stack_store v16, ss1 + stack_store v16, ss1+16 + stack_store v16, ss1+32 + stack_store v16, ss1+48 + stack_store v16, ss1+64 + stack_store v15, ss1+80 ; v15 = 0 + stack_store v13, ss1+88 ; v13 = 0 + stack_store v16, ss2 + stack_store v16, ss2+16 + stack_store v16, ss2+32 + stack_store v16, ss2+48 + stack_store v16, ss2+64 + stack_store v15, ss2+80 ; v15 = 0 + stack_store v13, ss2+88 ; v13 = 0 + stack_store v16, ss3 + stack_store v16, ss3+16 + stack_store v16, ss3+32 + stack_store v16, ss3+48 + stack_store v16, ss3+64 + stack_store v15, ss3+80 ; v15 = 0 + stack_store v13, ss3+88 ; v13 = 0 + stack_store v16, ss4 + stack_store v16, ss4+16 + stack_store v16, ss4+32 + stack_store v16, ss4+48 + stack_store v16, ss4+64 + stack_store v16, ss4+80 + stack_store v16, ss4+96 + stack_store v15, ss4+112 ; v15 = 0 + stack_store v14, ss4+120 ; v14 = 0 + stack_store v13, ss4+124 ; v13 = 0 + stack_store v16, ss5 + stack_store v16, ss5+16 + stack_store v16, ss5+32 + stack_store v16, ss5+48 + stack_store v16, ss5+64 + stack_store v16, ss5+80 + stack_store v16, ss5+96 + stack_store v15, ss5+112 ; v15 = 0 + stack_store v14, ss5+120 ; v14 = 0 + stack_store v13, ss5+124 ; v13 = 0 + stack_store v16, ss6 + stack_store v16, ss6+16 + stack_store v16, ss6+32 + stack_store v16, ss6+48 + stack_store v16, ss6+64 + stack_store v16, ss6+80 + stack_store v16, ss6+96 + stack_store v15, ss6+112 ; v15 = 0 + stack_store v14, ss6+120 ; v14 = 0 + stack_store v13, ss6+124 ; v13 = 0 + stack_store v16, ss7 + stack_store v16, ss7+16 + stack_store v16, ss7+32 + stack_store v16, ss7+48 + stack_store v16, ss7+64 + stack_store v16, ss7+80 + stack_store v16, ss7+96 + stack_store v15, ss7+112 ; v15 = 0 + stack_store v14, ss7+120 ; v14 = 0 + stack_store v13, ss7+124 ; v13 = 0 + + + v17 = select_spectre_guard v8, v0, v0 + v18 = isub v8, v8 + + return v1, v3, v2, v17, v1, v1, v18, v17, v6 +} + +; run: %a(64324483005384539584200704, 0, 0, 95, 24415, 1600085839, 1, 0, 89294900846985228, 4) == [0, 95, 0, 64324483005384539584200704, 0, 0, 0, 64324483005384539584200704, 1]