T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add 8-bit variation of adjust_sp_imm for 32-bit and 64-bit Intel.

Browse Source
This commit is contained in:
Tyler McMullen
2017-12-05 10:56:22 -08:00
committed by Jakob Stoklund Olesen
parent 3b937f5917
commit 7988d0c54c
4 changed files with 28 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
cranelift/filetests/isa/intel/binary32.cton
View File

@@ -390,13 +390,17 @@ ebb0:
[-,%rcx] v512 = x86_pop.i32 ; bin: 59 [-,%rcx] v512 = x86_pop.i32 ; bin: 59
; Adjust Stack Pointer ; Adjust Stack Pointer
; asm: addq $1024, %rsp ; asm: addl $64, %esp
adjust_sp_imm 64 ; bin: 83 c4 40
; asm: addl $-64, %esp
adjust_sp_imm -64 ; bin: 83 c4 c0
; asm: addl $1024, %esp
adjust_sp_imm 1024 ; bin: 81 c4 00000400 adjust_sp_imm 1024 ; bin: 81 c4 00000400
; asm: addq $-1024, %rsp ; asm: addl $-1024, %esp
adjust_sp_imm -1024 ; bin: 81 c4 fffffc00 adjust_sp_imm -1024 ; bin: 81 c4 fffffc00
; asm: addq $2147483647, %rsp ; asm: addl $2147483647, %esp
adjust_sp_imm 2147483647 ; bin: 81 c4 7fffffff adjust_sp_imm 2147483647 ; bin: 81 c4 7fffffff
; asm: addq $-2147483648, %rsp ; asm: addl $-2147483648, %esp
adjust_sp_imm -2147483648 ; bin: 81 c4 80000000 adjust_sp_imm -2147483648 ; bin: 81 c4 80000000

4
cranelift/filetests/isa/intel/binary64.cton
View File

@@ -494,6 +494,10 @@ ebb0:
[-,%r10] v514 = x86_pop.i64 ; bin: 41 5a [-,%r10] v514 = x86_pop.i64 ; bin: 41 5a
; Adjust Stack Pointer ; Adjust Stack Pointer
; asm: addq $64, %rsp
adjust_sp_imm 64 ; bin: 48 83 c4 40
; asm: addq $-64, %rsp
adjust_sp_imm -64 ; bin: 48 83 c4 c0
; asm: addq $1024, %rsp ; asm: addq $1024, %rsp
adjust_sp_imm 1024 ; bin: 48 81 c4 00000400 adjust_sp_imm 1024 ; bin: 48 81 c4 00000400
; asm: addq $-1024, %rsp ; asm: addq $-1024, %rsp

6
lib/cretonne/meta/isa/intel/encodings.py
View File

@@ -239,8 +239,10 @@ I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
I32.enc(base.copy_special, *r.copysp(0x89)) I32.enc(base.copy_special, *r.copysp(0x89))
# Adjust SP Imm # Adjust SP Imm
I32.enc(base.adjust_sp_imm, *r.adjustsp(0x81)) I32.enc(base.adjust_sp_imm, *r.adjustsp8(0x83))
I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1)) I32.enc(base.adjust_sp_imm, *r.adjustsp32(0x81))
I64.enc(base.adjust_sp_imm, *r.adjustsp8.rex(0x83, w=1))
I64.enc(base.adjust_sp_imm, *r.adjustsp32.rex(0x81, w=1))
# #
# Float loads and stores. # Float loads and stores.

14
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -493,8 +493,18 @@ copysp = TailRecipe(
modrm_rr(dst, src, sink); modrm_rr(dst, src, sink);
''') ''')
adjustsp = TailRecipe( adjustsp8 = TailRecipe(
'adjustsp', UnaryImm, size=5, ins=(), outs=(), 'adjustsp8', UnaryImm, size=2, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 8),
emit='''
PUT_OP(bits, rex1(4), sink);
modrm_r_bits(4, bits, sink);
let imm: i64 = imm.into();
sink.put1(imm as u8);
''')
adjustsp32 = TailRecipe(
'adjustsp32', UnaryImm, size=5, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 32), instp=IsSignedInt(UnaryImm.imm, 32),
emit=''' emit='''
PUT_OP(bits, rex1(4), sink); PUT_OP(bits, rex1(4), sink);