From 7988d0c54cbad0ec0545706cbd781dee425a1eb3 Mon Sep 17 00:00:00 2001
From: Tyler McMullen <tyler@fastly.com>
Date: Tue, 5 Dec 2017 10:56:22 -0800
Subject: [PATCH] Add 8-bit variation of adjust_sp_imm for 32-bit and 64-bit
 Intel.

---
 cranelift/filetests/isa/intel/binary32.cton | 12 ++++++++----
 cranelift/filetests/isa/intel/binary64.cton |  4 ++++
 lib/cretonne/meta/isa/intel/encodings.py    |  6 ++++--
 lib/cretonne/meta/isa/intel/recipes.py      | 14 ++++++++++++--
 4 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 41d364c63d..02e7fc0364 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -390,13 +390,17 @@ ebb0:
     [-,%rcx]            v512 = x86_pop.i32      ; bin: 59
 
     ; Adjust Stack Pointer
-    ; asm: addq $1024, %rsp
+    ; asm: addl $64, %esp
+    adjust_sp_imm 64                            ; bin: 83 c4 40
+    ; asm: addl $-64, %esp
+    adjust_sp_imm -64                           ; bin: 83 c4 c0
+    ; asm: addl $1024, %esp
     adjust_sp_imm 1024                          ; bin: 81 c4 00000400
-    ; asm: addq $-1024, %rsp
+    ; asm: addl $-1024, %esp
     adjust_sp_imm -1024                         ; bin: 81 c4 fffffc00
-    ; asm: addq $2147483647, %rsp
+    ; asm: addl $2147483647, %esp
     adjust_sp_imm 2147483647                    ; bin: 81 c4 7fffffff
-    ; asm: addq $-2147483648, %rsp
+    ; asm: addl $-2147483648, %esp
     adjust_sp_imm -2147483648                   ; bin: 81 c4 80000000
 
 
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 6af8f91a89..719e6b1de5 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -494,6 +494,10 @@ ebb0:
     [-,%r10]            v514 = x86_pop.i64      ; bin: 41 5a
 
     ; Adjust Stack Pointer
+    ; asm: addq $64, %rsp
+    adjust_sp_imm 64                            ; bin: 48 83 c4 40
+    ; asm: addq $-64, %rsp
+    adjust_sp_imm -64                           ; bin: 48 83 c4 c0
     ; asm: addq $1024, %rsp
     adjust_sp_imm 1024                          ; bin: 48 81 c4 00000400
     ; asm: addq $-1024, %rsp
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index fed3d10c17..52a56a514d 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -239,8 +239,10 @@ I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
 I32.enc(base.copy_special, *r.copysp(0x89))
 
 # Adjust SP Imm
-I32.enc(base.adjust_sp_imm, *r.adjustsp(0x81))
-I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1))
+I32.enc(base.adjust_sp_imm, *r.adjustsp8(0x83))
+I32.enc(base.adjust_sp_imm, *r.adjustsp32(0x81))
+I64.enc(base.adjust_sp_imm, *r.adjustsp8.rex(0x83, w=1))
+I64.enc(base.adjust_sp_imm, *r.adjustsp32.rex(0x81, w=1))
 
 #
 # Float loads and stores.
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index be15c3053d..e4ae7c74c4 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -493,8 +493,18 @@ copysp = TailRecipe(
         modrm_rr(dst, src, sink);
         ''')
 
-adjustsp = TailRecipe(
-    'adjustsp', UnaryImm, size=5, ins=(), outs=(),
+adjustsp8 = TailRecipe(
+    'adjustsp8', UnaryImm, size=2, ins=(), outs=(),
+    instp=IsSignedInt(UnaryImm.imm, 8),
+    emit='''
+    PUT_OP(bits, rex1(4), sink);
+    modrm_r_bits(4, bits, sink);
+    let imm: i64 = imm.into();
+    sink.put1(imm as u8);
+    ''')
+
+adjustsp32 = TailRecipe(
+    'adjustsp32', UnaryImm, size=5, ins=(), outs=(),
     instp=IsSignedInt(UnaryImm.imm, 32),
     emit='''
     PUT_OP(bits, rex1(4), sink);