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Add 8-bit variation of adjust_sp_imm for 32-bit and 64-bit Intel.

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This commit is contained in:
Tyler McMullen
2017-12-05 10:56:22 -08:00
committed by Jakob Stoklund Olesen
parent 3b937f5917
commit 7988d0c54c
4 changed files with 28 additions and 8 deletions
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6
lib/cretonne/meta/isa/intel/encodings.py
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@@ -239,8 +239,10 @@ I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
I32.enc(base.copy_special, *r.copysp(0x89))
# Adjust SP Imm
I32.enc(base.adjust_sp_imm, *r.adjustsp(0x81))
I64.enc(base.adjust_sp_imm, *r.adjustsp.rex(0x81, w=1))
I32.enc(base.adjust_sp_imm, *r.adjustsp8(0x83))
I32.enc(base.adjust_sp_imm, *r.adjustsp32(0x81))
I64.enc(base.adjust_sp_imm, *r.adjustsp8.rex(0x83, w=1))
I64.enc(base.adjust_sp_imm, *r.adjustsp32.rex(0x81, w=1))
#
# Float loads and stores.

14
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -493,8 +493,18 @@ copysp = TailRecipe(
modrm_rr(dst, src, sink);
''')
adjustsp = TailRecipe(
'adjustsp', UnaryImm, size=5, ins=(), outs=(),
adjustsp8 = TailRecipe(
'adjustsp8', UnaryImm, size=2, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 8),
emit='''
PUT_OP(bits, rex1(4), sink);
modrm_r_bits(4, bits, sink);
let imm: i64 = imm.into();
sink.put1(imm as u8);
''')
adjustsp32 = TailRecipe(
'adjustsp32', UnaryImm, size=5, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 32),
emit='''
PUT_OP(bits, rex1(4), sink);