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Add Intel encodings for ifcmp_sp.

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Also generate an Into<RegUnit> implementation for the RU enums.
This commit is contained in:
Jakob Stoklund Olesen
2018-02-09 14:32:29 -08:00
parent 73c4c356c9
commit 788a78caf4
9 changed files with 34 additions and 8 deletions
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2
lib/cretonne/src/isa/arm32/registers.rs
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@@ -1,6 +1,6 @@
//! ARM32 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));

2
lib/cretonne/src/isa/arm64/registers.rs
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@@ -1,6 +1,6 @@
//! ARM64 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));

2
lib/cretonne/src/isa/intel/registers.rs
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@@ -1,6 +1,6 @@
//! Intel register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-intel.rs"));

2
lib/cretonne/src/isa/riscv/registers.rs
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@@ -1,6 +1,6 @@
//! RISC-V register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));