diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 5da0c709a6..e507e5fbcd 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -534,5 +534,11 @@ ebb1:
     ; asm: jnbe .+4; ud2
     trapif ule v11, user0                          ; bin: 77 02 0f 0b
 
+    ; Stack check.
+    ; asm: cmpl %esp, %ecx
+    [-,%eflags]         v40 = ifcmp_sp v1       ; bin: 39 e1
+    ; asm: cmpl %esp, %esi
+    [-,%eflags]         v41 = ifcmp_sp v2       ; bin: 39 e6
+
     return
 }
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 29f75085d9..486223ec6f 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -615,6 +615,12 @@ ebb1:
     ; asm: jnbe .+4; ud2
     trapif ule v11, user0                          ; bin: 77 02 0f 0b
 
+    ; Stack check.
+    ; asm: cmpq %rsp, %rcx
+    [-,%eflags]         v40 = ifcmp_sp v1       ; bin: 48 39 e1
+    ; asm: cmpq %rsp, %r10
+    [-,%eflags]         v41 = ifcmp_sp v2       ; bin: 49 39 e2
+
     return
 }
 
diff --git a/lib/cretonne/meta/gen_registers.py b/lib/cretonne/meta/gen_registers.py
index 8e12fbf34f..166bc611da 100644
--- a/lib/cretonne/meta/gen_registers.py
+++ b/lib/cretonne/meta/gen_registers.py
@@ -96,6 +96,9 @@ def gen_isa(isa, fmt):
     with fmt.indented('pub enum RU {', '}'):
         for regbank in isa.regbanks:
             gen_regbank_units(regbank, fmt)
+    with fmt.indented('impl Into<RegUnit> for RU {', '}'):
+        with fmt.indented('fn into(self) -> RegUnit {', '}'):
+            fmt.line('self as RegUnit')
 
 
 def generate(isas, out_dir):
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 5b9f8ae422..449e159f71 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -364,6 +364,9 @@ I64.enc(base.trapif, r.trapif, 0)
 enc_i32_i64(base.icmp, r.icscc, 0x39)
 enc_i32_i64(base.ifcmp, r.rcmp, 0x39)
 
+I32.enc(base.ifcmp_sp.i32, *r.rcmp_sp(0x39))
+I64.enc(base.ifcmp_sp.i64, *r.rcmp_sp.rex(0x39, w=1))
+
 #
 # Convert flags to bool.
 #
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 7e74abae47..56f67306cb 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -517,8 +517,8 @@ adjustsp8 = TailRecipe(
     'adjustsp8', UnaryImm, size=2, ins=(), outs=(),
     instp=IsSignedInt(UnaryImm.imm, 8),
     emit='''
-    PUT_OP(bits, rex1(4), sink);
-    modrm_r_bits(4, bits, sink);
+    PUT_OP(bits, rex1(RU::rsp.into()), sink);
+    modrm_r_bits(RU::rsp.into(), bits, sink);
     let imm: i64 = imm.into();
     sink.put1(imm as u8);
     ''')
@@ -527,8 +527,8 @@ adjustsp32 = TailRecipe(
     'adjustsp32', UnaryImm, size=5, ins=(), outs=(),
     instp=IsSignedInt(UnaryImm.imm, 32),
     emit='''
-    PUT_OP(bits, rex1(4), sink);
-    modrm_r_bits(4, bits, sink);
+    PUT_OP(bits, rex1(RU::rsp.into()), sink);
+    modrm_r_bits(RU::rsp.into(), bits, sink);
     let imm: i64 = imm.into();
     sink.put4(imm as u32);
     ''')
@@ -1081,6 +1081,14 @@ fcmp = TailRecipe(
         modrm_rr(in_reg1, in_reg0, sink);
         ''')
 
+# Same as rcmp, but second operand is the stack pointer.
+rcmp_sp = TailRecipe(
+        'rcmp_sp', Unary, size=1, ins=GPR, outs=FLAG.eflags,
+        emit='''
+        PUT_OP(bits, rex2(in_reg0, RU::rsp.into()), sink);
+        modrm_rr(in_reg0, RU::rsp.into(), sink);
+        ''')
+
 # Test-and-branch.
 #
 # This recipe represents the macro fusion of a test and a conditional branch.
diff --git a/lib/cretonne/src/isa/arm32/registers.rs b/lib/cretonne/src/isa/arm32/registers.rs
index 283f113d1e..7c6ac406e1 100644
--- a/lib/cretonne/src/isa/arm32/registers.rs
+++ b/lib/cretonne/src/isa/arm32/registers.rs
@@ -1,6 +1,6 @@
 //! ARM32 register descriptions.
 
-use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
+use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
 
 include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));
 
diff --git a/lib/cretonne/src/isa/arm64/registers.rs b/lib/cretonne/src/isa/arm64/registers.rs
index d4cee48891..62311aaebe 100644
--- a/lib/cretonne/src/isa/arm64/registers.rs
+++ b/lib/cretonne/src/isa/arm64/registers.rs
@@ -1,6 +1,6 @@
 //! ARM64 register descriptions.
 
-use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
+use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
 
 include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));
 
diff --git a/lib/cretonne/src/isa/intel/registers.rs b/lib/cretonne/src/isa/intel/registers.rs
index fcb1cf4445..c2b96f77d3 100644
--- a/lib/cretonne/src/isa/intel/registers.rs
+++ b/lib/cretonne/src/isa/intel/registers.rs
@@ -1,6 +1,6 @@
 //! Intel register descriptions.
 
-use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
+use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
 
 include!(concat!(env!("OUT_DIR"), "/registers-intel.rs"));
 
diff --git a/lib/cretonne/src/isa/riscv/registers.rs b/lib/cretonne/src/isa/riscv/registers.rs
index 9447e5ea29..3cce8c4988 100644
--- a/lib/cretonne/src/isa/riscv/registers.rs
+++ b/lib/cretonne/src/isa/riscv/registers.rs
@@ -1,6 +1,6 @@
 //! RISC-V register descriptions.
 
-use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
+use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
 
 include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));