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Add Intel encodings for ifcmp_sp.

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Also generate an Into<RegUnit> implementation for the RU enums.
This commit is contained in:
Jakob Stoklund Olesen
2018-02-09 14:32:29 -08:00
parent 73c4c356c9
commit 788a78caf4
9 changed files with 34 additions and 8 deletions
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3
lib/cretonne/meta/gen_registers.py
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@@ -96,6 +96,9 @@ def gen_isa(isa, fmt):
with fmt.indented('pub enum RU {', '}'):
for regbank in isa.regbanks:
gen_regbank_units(regbank, fmt)
with fmt.indented('impl Into<RegUnit> for RU {', '}'):
with fmt.indented('fn into(self) -> RegUnit {', '}'):
fmt.line('self as RegUnit')
def generate(isas, out_dir):

3
lib/cretonne/meta/isa/intel/encodings.py
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@@ -364,6 +364,9 @@ I64.enc(base.trapif, r.trapif, 0)
enc_i32_i64(base.icmp, r.icscc, 0x39)
enc_i32_i64(base.ifcmp, r.rcmp, 0x39)
I32.enc(base.ifcmp_sp.i32, *r.rcmp_sp(0x39))
I64.enc(base.ifcmp_sp.i64, *r.rcmp_sp.rex(0x39, w=1))
#
# Convert flags to bool.
#

16
lib/cretonne/meta/isa/intel/recipes.py
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@@ -517,8 +517,8 @@ adjustsp8 = TailRecipe(
'adjustsp8', UnaryImm, size=2, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 8),
emit='''
PUT_OP(bits, rex1(4), sink);
modrm_r_bits(4, bits, sink);
PUT_OP(bits, rex1(RU::rsp.into()), sink);
modrm_r_bits(RU::rsp.into(), bits, sink);
let imm: i64 = imm.into();
sink.put1(imm as u8);
''')
@@ -527,8 +527,8 @@ adjustsp32 = TailRecipe(
'adjustsp32', UnaryImm, size=5, ins=(), outs=(),
instp=IsSignedInt(UnaryImm.imm, 32),
emit='''
PUT_OP(bits, rex1(4), sink);
modrm_r_bits(4, bits, sink);
PUT_OP(bits, rex1(RU::rsp.into()), sink);
modrm_r_bits(RU::rsp.into(), bits, sink);
let imm: i64 = imm.into();
sink.put4(imm as u32);
''')
@@ -1081,6 +1081,14 @@ fcmp = TailRecipe(
modrm_rr(in_reg1, in_reg0, sink);
''')
# Same as rcmp, but second operand is the stack pointer.
rcmp_sp = TailRecipe(
'rcmp_sp', Unary, size=1, ins=GPR, outs=FLAG.eflags,
emit='''
PUT_OP(bits, rex2(in_reg0, RU::rsp.into()), sink);
modrm_rr(in_reg0, RU::rsp.into(), sink);
''')
# Test-and-branch.
#
# This recipe represents the macro fusion of a test and a conditional branch.

2
lib/cretonne/src/isa/arm32/registers.rs
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@@ -1,6 +1,6 @@
//! ARM32 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));

2
lib/cretonne/src/isa/arm64/registers.rs
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@@ -1,6 +1,6 @@
//! ARM64 register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));

2
lib/cretonne/src/isa/intel/registers.rs
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@@ -1,6 +1,6 @@
//! Intel register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-intel.rs"));

2
lib/cretonne/src/isa/riscv/registers.rs
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@@ -1,6 +1,6 @@
//! RISC-V register descriptions.
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo};
use isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));