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Make the stackslot offsets available for debuginfo

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This commit is contained in:
bjorn3
2021-02-03 15:59:00 +01:00
parent 256cc8a518
commit 76d615049d
7 changed files with 31 additions and 14 deletions
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2
cranelift/codegen/src/isa/aarch64/mod.rs
View File

@@ -66,6 +66,7 @@ impl MachBackend for AArch64Backend {
let buffer = vcode.emit();
let frame_size = vcode.frame_size();
let unwind_info = vcode.unwind_info()?;
let stackslot_offsets = vcode.stackslot_offsets().clone();
let disasm = if want_disasm {
Some(vcode.show_rru(Some(&create_reg_universe(flags))))
@@ -81,6 +82,7 @@ impl MachBackend for AArch64Backend {
disasm,
unwind_info,
value_labels_ranges: None,
stackslot_offsets,
})
}

2
cranelift/codegen/src/isa/arm32/mod.rs
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@@ -61,6 +61,7 @@ impl MachBackend for Arm32Backend {
let vcode = self.compile_vcode(func, flags.clone())?;
let buffer = vcode.emit();
let frame_size = vcode.frame_size();
let stackslot_offsets = vcode.stackslot_offsets().clone();
let disasm = if want_disasm {
Some(vcode.show_rru(Some(&create_reg_universe())))
@@ -76,6 +77,7 @@ impl MachBackend for Arm32Backend {
disasm,
unwind_info: None,
value_labels_ranges: None,
stackslot_offsets,
})
}

4
cranelift/codegen/src/isa/x64/mod.rs
View File

@@ -62,7 +62,8 @@ impl MachBackend for X64Backend {
let buffer = buffer.finish();
let frame_size = vcode.frame_size();
let unwind_info = vcode.unwind_info()?;
let value_labels_ranges = vcode.value_labels_ranges()?;
let value_labels_ranges = vcode.value_labels_ranges();
let stackslot_offsets = vcode.stackslot_offsets().clone();
let disasm = if want_disasm {
Some(vcode.show_rru(Some(&create_reg_universe_systemv(flags))))
@@ -76,6 +77,7 @@ impl MachBackend for X64Backend {
disasm,
unwind_info,
value_labels_ranges,
stackslot_offsets,
})
}

3
cranelift/codegen/src/machinst/abi.rs
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@@ -57,6 +57,9 @@ pub trait ABICallee {
/// Number of stack slots (not spill slots).
fn num_stackslots(&self) -> usize;
/// The offsets of all stack slots (not spill slots) for debuginfo purposes.
fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32>;
/// Generate an instruction which copies an argument to a destination
/// register.
fn gen_copy_arg_to_regs(

14
cranelift/codegen/src/machinst/abi_impl.rs
View File

@@ -506,7 +506,7 @@ pub struct ABICalleeImpl<M: ABIMachineSpec> {
/// Signature: arg and retval regs.
sig: ABISig,
/// Offsets to each stackslot.
stackslots: Vec<u32>,
stackslots: PrimaryMap<StackSlot, u32>,
/// Total stack size of all stackslots.
stackslots_size: u32,
/// Stack size to be reserved for outgoing arguments.
@@ -584,7 +584,7 @@ impl<M: ABIMachineSpec> ABICalleeImpl<M> {
// Compute stackslot locations and total stackslot size.
let mut stack_offset: u32 = 0;
let mut stackslots = vec![];
let mut stackslots = PrimaryMap::new();
for (stackslot, data) in f.stack_slots.iter() {
let off = stack_offset;
stack_offset += data.size;
@@ -926,6 +926,10 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
self.stackslots.len()
}
fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
&self.stackslots
}
fn gen_copy_arg_to_regs(
&self,
idx: usize,
@@ -1101,7 +1105,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
) -> SmallInstVec<Self::I> {
// Offset from beginning of stackslot area, which is at nominal SP (see
// [MemArg::NominalSPOffset] for more details on nominal SP tracking).
let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
let stack_off = self.stackslots[slot] as i64;
let sp_off: i64 = stack_off + (offset as i64);
trace!("load_stackslot: slot {} -> sp_off {}", slot, sp_off);
gen_load_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), into_regs, ty)
@@ -1117,7 +1121,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
) -> SmallInstVec<Self::I> {
// Offset from beginning of stackslot area, which is at nominal SP (see
// [MemArg::NominalSPOffset] for more details on nominal SP tracking).
let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
let stack_off = self.stackslots[slot] as i64;
let sp_off: i64 = stack_off + (offset as i64);
trace!("store_stackslot: slot {} -> sp_off {}", slot, sp_off);
gen_store_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), from_regs, ty)
@@ -1127,7 +1131,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
fn stackslot_addr(&self, slot: StackSlot, offset: u32, into_reg: Writable<Reg>) -> Self::I {
// Offset from beginning of stackslot area, which is at nominal SP (see
// [MemArg::NominalSPOffset] for more details on nominal SP tracking).
let stack_off = self.stackslots[slot.as_u32() as usize] as i64;
let stack_off = self.stackslots[slot] as i64;
let sp_off: i64 = stack_off + (offset as i64);
M::gen_get_stack_addr(StackAMode::NominalSPOffset(sp_off, I8), into_reg, I8)
}

5
cranelift/codegen/src/machinst/mod.rs
View File

@@ -62,7 +62,7 @@
use crate::binemit::{CodeInfo, CodeOffset, StackMap};
use crate::ir::condcodes::IntCC;
use crate::ir::{Function, SourceLoc, Type, ValueLabel};
use crate::ir::{Function, SourceLoc, StackSlot, Type, ValueLabel};
use crate::isa::unwind::input as unwind_input;
use crate::result::CodegenResult;
use crate::settings::Flags;
@@ -71,6 +71,7 @@ use alloc::boxed::Box;
use alloc::vec::Vec;
use core::fmt::Debug;
use core::ops::Range;
use cranelift_entity::PrimaryMap;
use regalloc::RegUsageCollector;
use regalloc::{
RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
@@ -343,6 +344,8 @@ pub struct MachCompileResult {
pub unwind_info: Option<unwind_input::UnwindInfo<Reg>>,
/// Debug info: value labels to registers/stackslots at code offsets.
pub value_labels_ranges: Option<ValueLabelsRanges>,
/// Debug info: stackslots to stack pointer offsets.
pub stackslot_offsets: PrimaryMap<StackSlot, u32>,
}
impl MachCompileResult {

15
cranelift/codegen/src/machinst/vcode.rs
View File

@@ -617,17 +617,18 @@ impl<I: VCodeInst> VCode<I> {
}
/// Generates value-label ranges.
pub fn value_labels_ranges(&self) -> crate::result::CodegenResult<Option<ValueLabelsRanges>> {
pub fn value_labels_ranges(&self) -> Option<ValueLabelsRanges> {
if !self.has_value_labels {
return Ok(None);
return None;
}
let layout = &self.insts_layout.borrow();
Ok(Some(debug::compute(
&self.insts,
&layout.0[..],
&layout.1[..],
)))
Some(debug::compute(&self.insts, &layout.0[..], &layout.1[..]))
}
/// Get the offsets of stackslots.
pub fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
self.abi.stackslot_offsets()
}
/// Get the IR block for a BlockIndex, if one exists.